Semiconductor structure

ABSTRACT

A semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

This application claims the benefit of U.S. provisional application Ser. No. 63/395,887, filed Aug. 8, 2022, the disclosures of which are incorporated by reference herein in its entirety.

TECHNICAL FIELD

The disclosure relates in general to a semiconductor structure.

BACKGROUND

The advent of 5G and AI has spurred a plethora of new end use applications in 3 Cs, namely, high-performance computing (HPC), data centers (i.e., cloud), base stations (i.e., connectivity), commercial/edge electronics (i.e., client/edge) and AI covering all 3 Cs, leading to high semiconductor growth and an exponential growth in data communication. According to Cisco Global Cloud Index, the annual global data center IP traffic will surpass an astounding 20 zettabytes (20×10²¹ bytes) by 2021, which was >3× growth from 6.8 zettabytes for 2016. Semiconductor devices that target the high-performance computing (HPC), data center and artificial intelligence (AI) markets have always represented the prevalent state-of-the-art when it comes to integrated circuits (ICs) and IC packaging technologies. The same also holds true for high-end smart handheld applications.

The skyrocketing data traffic demands advanced ICs, particularly processors and memories, and advanced system-in-a-package (SiP) packaging in the extreme for high HPC, data centers, AI, high-end smart handheld and 5G/6G applications. This, in turn, has propelled the following four industry disruptions covering IC, package and system levels which are taking place simultaneously: (a) from ever-larger processor system-on-chip (SoC) die to disaggregated small die based chiplets-in-SiP, (b) from traditional computing to near-memory computing to in-memory computing to reduce the memory wall between processor and memory at the system level in order to more fully exploit the processor performance potentials; (c) from copper interconnect to optical interconnect, and (d) from advanced organic laminate substrates to silicon interposers and hybrid substrates with embedded active and passive devices. SoC is an IC that integrates all or most components of a computer including almost always a central processing unit (CPU), memory, input/output ports and secondary storage, whereas SiP is defined an IC package containing more than one active device such as an IC or a MEMS (micro-electromechanical system). Extreme advanced SiP packaging of high-end processors and memories with fanout (for smart handhelds), 2.5D IC, 3D IC, embedded SiP and silicon photonics in particular has been and will continue to be the primary enabler of all four disruptions as well as continuation of IC performance advancement for advanced IC applications covering 3 Cs, leading to unprecedented levels of heterogeneous integration at the IC, package and system levels going forward.

In order to deliver ever-higher performance to process the exponential increase in data traffic, processor chip power at data centers is expected to grow 5 times from 2018 to 2025, reaching 1000 W per chip with chips packaged in 2.50 IC, 3D IC and/or chiplets-in-SiP platforms. Certain AI applications such as Cerebra's 8″×8″ wafer-scale AI processor chip, the largest SoC ever built, already consumes an astounding 15 KW per chip. According to an article published in Nature, “How to Stop Data Centers from Gobbling up the World's Electricity” (Sep. 12, 2018), the energy consumption of data centers and communication networks will reach 17% of total electricity demand worldwide by 2030. Data center power consumption and related chips' thermal management is expected to continue to limit the full potential of the cloud and 5G/6G digital world/economy applications as the industry struggles with power and cooling (by, for example, air, direct-to-chip liquid cooling and/or liquid immersion). In addition to escalating power consumption, data center power density requirements continue to increase year after year. The average rack power density is currently around 7-16 k W. With HPC and data centers, power densities may reach 100 k W per rack.

Data centers is maxing out on how much heat they may dissipate for applications such as servers (which drive 40 percent of the power used in data centers), network interface cards (NICs), and fiber-optic transceivers, as well as on the trade-offs between switching speed and power efficiency. Power management also presents a challenge for small devices requiring extremely high densities such as optical transceivers (and silicon photonics) as power supplies are bulky and too far away from them due to their large sizes.

The above market impetus together with the recently demonstrated ability of the grown diamond industry to grow larger, higher-quality, electronic grade diamond films (typically by microwave plasma-assisted chemical vapor deposition, CVD) present an excellent opportunity for diamond (both polycrystalline diamond, PCD, and single crystal diamond, SCD) and more so for silicon (Si)-diamond and SiC (silicon carbide)-diamond composite wafers (e.g., bi-wafers and tri-wafers) to be implemented to create a new breed of advanced ICs and advanced SiPs for the aforementioned high power and 5G/6G applications, taking advantage of diamond's “extreme” properties, notably, extreme thermal conductivity, TC (˜24 W/cm·K) which is >5× that of copper, extremely high breakdown field (˜20 MV/cm), and extremely low thermal expansion coefficient (˜1 ppm/° C. at room temperature). Diamond possesses the highest TC among all materials on Earth.

SUMMARY

According to an embodiment, a method to form a first diamond composite wafer, a second diamond composite wafer or a third diamond composite wafer with a first predetermined diameter includes the following steps: preparing a plurality of diamond blocks, wherein a dimension of each diamond block is smaller than the first predetermined diameter; attaching the plurality of diamond blocks to a first semiconductor substrate with the first predetermined diameter to form a first temporary composite wafer, wherein a thermal conductivity of the first semiconductor substrate is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks of the first temporary composite wafer to form the first diamond composite wafer; attaching the first diamond composite wafer to a second semiconductor substrate with the first predetermined diameter to form the second diamond composite wafer, and/or removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer.

According to another embodiment, a method to form a first diamond composite wafer, a second diamond composite wafer, a third diamond composite wafer or a fourth diamond composite wafer with a first predetermined diameter includes the following steps: depositing diamond on a second semiconductor substrate with a second predetermined diameter which is smaller than the first predetermined diameter to form a second temporary composite wafer, wherein a thermal conductivity of the second semiconductor substrate is smaller than that of diamond; attaching a plurality of the second temporary composite wafers to a first temporary carrier with the first predetermined diameter to form a first temporary composite wafer and filling gaps among the plurality of the second diamond composite wafers to form the first diamond composite wafer; attaching the first diamond composite wafer to a second semiconductor substrate with the first predetermined diameter to form the second diamond composite wafer, removing the first semiconductor substrate from the first diamond composite wafer to form the third diamond composite wafer, and/or removing the second semiconductor substrate from the second diamond composite wafer to form the fourth diamond composite wafer.

According to another embodiment, a method to form a first diamond composite wafer, a second diamond composite wafer, a third diamond composite wafer or a fourth diamond composite wafer with a first predetermined diameter, includes the following steps: attaching a plurality of diamond blocks and a plurality of semiconductor blocks to a first temporary carrier with the first predetermined diameter to form a first temporary composite wafer, wherein both a dimension of each diamond block and a dimension of each semiconductor block are smaller than the first predetermined diameter, and a thermal conductivity of the semiconductor block is smaller than that of the diamond block; and filling gaps among the plurality of diamond blocks and gaps among the plurality of semiconductor blocks, and removing the first temporary carrier to form the fourth diamond composite wafer; attaching the fourth diamond composite wafer to a first semiconductor substrate with the first predetermined diameter to form the second diamond composite wafer; removing the plurality of semiconductor blocks from the second diamond composite wafer to form the first diamond composite wafer; and/or removing the plurality of semiconductor blocks from the fourth diamond composite wafer to form the third diamond composite wafer.

According to another embodiment, a method to form a first diamond composite IC wafer or a second diamond composite IC wafer, includes the following steps: (a). preparing a first semiconductor wafer with a first predetermined diameter, wherein the first semiconductor wafer includes a set of IC circuits on a first side of the first semiconductor wafer; (b). preparing a plurality of diamond blocks wherein a dimension of each diamond block is smaller than the first predetermined diameter, or a diamond wafer with the first predetermined diameter; and (c). bonding the plurality of diamond blocks to the first semiconductor wafer, and filling gaps among the plurality of diamond blocks to form the first diamond composite IC wafer; or bonding the diamond wafer with the first predetermined diameter to the first semiconductor wafer to form the second diamond composite IC wafer.

According to another embodiment, a method to process a diamond composite wafer includes the following steps: (a). forming a plurality of through vias in the diamond composite wafer and a first re-distribution layer on a first side of the diamond composite wafer; (b). attaching a temporary carrier to the first re-distribution layer, and forming a second re-distribution layer on a second side of the diamond composite wafer; and (c). releasing the temporary carrier to form a circuit containing diamond composite wafer.

According to the first embodiment, a semiconductor structure includes a substrate and a first circuit containing composite block over the substrate. The first circuit containing composite block includes a through via therein and a re-distribution layer thereon. The first circuit containing composite block includes a semiconductor block and a diamond block.

According to the second embodiment based on the first embodiment, the semiconductor structure further includes a second circuit containing composite block under the first circuit containing composite block. The second circuit containing composite block includes a through via therein and a re-distribution layer thereon. The second circuit containing composite block includes a semiconductor block and/or a diamond block.

According to the third embodiment based on the second embodiment, the first circuit containing composite block or the second circuit containing composite block further comprises a plurality of IC circuits.

According to the fourth embodiment based on the first embodiment, the through via is an electrical via, an optical via, a thermal via or a fluidic via.

According to the fifth embodiment based on the first embodiment, the re-distribution layer comprises an electrical interconnection or an optical waveguide.

According to the sixth embodiment, a semiconductor structure includes a substrate, a first circuit containing composite block over the substrate, and a cold plate bonded to the first circuit containing composite block. The first circuit containing composite block includes a first semiconductor block and a first diamond block, the first circuit containing composite block includes a first through via therein, and a first set of IC circuit in the first semiconductor block.

According to the seventh embodiment based on the sixth embodiment, the semiconductor structure further includes an interposer above the substrate and under the first circuit containing composite block, wherein the interposer comprises a fluidic via.

According to the eighth embodiment based on the seventh embodiment, the semiconductor structure further includes a second circuit containing composite block bonded to the first circuit containing composite block; wherein the second circuit containing composite block includes a second semiconductor block and a second diamond block, the second circuit containing composite block includes a second through via therein.

According to the ninth embodiment based on the eighth embodiment, a diamond layer is between the cold plate and the first circuit containing composite block.

According to the tenth embodiment based on the eighth embodiment, the semiconductor structure further includes a structural member surrounding the first circuit containing composite block and the second circuit containing composite block, wherein the structural member includes a fluidic channel fluidly coupled to the fluidic via of the interposer.

According to the 11^(th) embodiment based on the tenth embodiment, the semiconductor structure further includes a micro-jet coupled to the first circuit containing composite block.

According to the 12^(th) embodiment based on the tenth embodiment, the semiconductor structure further includes a dielectric liquid coolant filled between the structural member and the first circuit containing composite block.

According to the 13^(th) embodiment based on the 11^(th) embodiment, the second circuit containing composite block is bonded to the first circuit containing composite block through oxide-to-oxide bonding or polyimide (PI)-to-PI bonding.

According to the 14^(th) embodiment, a semiconductor structure includes a substrate, a first semiconductor block over the substrate, a second semiconductor block bonded to the first semiconductor block, and an interposer above the substrate and under the second semiconductor block. The first semiconductor block includes a first set of IC circuit. The second semiconductor block includes a second set of IC circuit. The interposer includes a fluidic via.

According to the 15^(th) embodiment based on the 14^(th) embodiment, the semiconductor structure further includes a cold plate bonded to the first semiconductor block.

According to the 16^(th) embodiment, a semiconductor structure includes a substrate, a first semiconductor block over the substrate and a second semiconductor block bonded to the first semiconductor block. The first semiconductor block includes a first set of IC circuit and a first fluidic channel. The second semiconductor block includes a second set of IC circuit and a second fluidic channel.

The above and other aspects of the disclosure will become better understood with regard to the following detailed description of the preferred but non-limiting embodiment (s). The following description is made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of a diamond composite wafer 100 according to an embodiment of the present disclosure;

FIG. 1B is a schematic diagram of a cross-sectional view of the diamond composite wafer of FIG. 1A in a direction 1B-1B′;

FIG. 2 is a cross-sectional view of a schematic diagram of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 8 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 9 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 10 is a schematic diagram of a cross-sectional view of a diamond composite wafer according to another embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a cross-sectional view of a diamond composite sub-assembly according to another embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIG. 15 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIGS. 16A to 16F are schematic diagrams of manufacturing processes of the diamond composite wafer of FIG. 2 according to an embodiment of the present disclosure;

FIGS. 17A to 17D are schematic diagrams of manufacturing processes of the diamond composite wafer of FIG. 5 according to an embodiment of the present disclosure;

FIGS. 18A to 18F are schematic diagrams of manufacturing processes of the diamond composite wafer of FIG. 5 according to another embodiment of the present disclosure;

FIGS. 19A to 19E are schematic diagrams of manufacturing processes of the diamond composite wafer of FIG. 9 according to an embodiment of the present disclosure;

FIGS. 20A to 20J are schematic diagrams of manufacturing processes of the diamond composite wafer of FIG. 9 according to another embodiment of the present disclosure;

FIGS. 21A to 21C are schematic diagrams of manufacturing processes of the diamond composite IC wafer of FIG. 12 according to an embodiment of the present disclosure;

FIGS. 22A to 22C are schematic diagrams of manufacturing processes of the diamond composite IC wafer of FIG. 12 according to another embodiment of the present disclosure;

FIGS. 23A to 23C are schematic diagrams of manufacturing processes of the diamond composite IC wafer of FIG. 13 according to another embodiment of the present disclosure;

FIGS. 24A to 24G are schematic diagrams of manufacturing processes of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIGS. 25A to 25G are schematic diagrams of manufacturing processes of a diamond composite IC wafer according to another embodiment of the present disclosure;

FIG. 26 is a schematic diagram of a wafer IC according to an embodiment of the present disclosure;

FIG. 27 is a schematic diagram of a wafer IC according to another embodiment of the present disclosure;

FIGS. 28A to 28E are schematic diagrams of manufacturing processes of the wafer IC of FIG. 26 according to an embodiment of the present disclosure;

FIGS. 29A to 29E are schematic diagrams of manufacturing processes of the wafer IC of FIG. 26 according to an embodiment of the present disclosure;

FIGS. 30A to 30E are schematic diagrams of manufacturing processes of the wafer IC of FIG. 27 according to another embodiment of the present disclosure;

FIG. 31 is a schematic diagram of a semiconductor structure 100B according to an embodiment of the present disclosure;

FIG. 32 is a schematic diagram of a semiconductor structure 100C according to another embodiment of the present disclosure;

FIG. 33 is a schematic diagram of a semiconductor structure 100D according to another embodiment of the present disclosure;

FIG. 34 is a schematic diagram of a semiconductor structure 100E according to another embodiment of the present disclosure;

FIG. 35 is a schematic diagram of a semiconductor structure 100F according to another embodiment of the present disclosure;

FIG. 36 is a schematic diagram of a semiconductor structure 100G according to another embodiment of the present disclosure;

FIG. 37 is a schematic diagram of a semiconductor structure 100H according to another embodiment of the present disclosure;

FIG. 38 is a schematic diagram of a semiconductor structure 100I according to another embodiment of the present disclosure;

FIG. 39 is a schematic diagram of a semiconductor structure 100J according to another embodiment of the present disclosure;

FIG. 40 is a schematic diagram of a semiconductor structure 100K according to another embodiment of the present disclosure;

FIG. 41 is a schematic diagram of a semiconductor structure 100L according to another embodiment of the present disclosure;

FIG. 42 is a schematic diagram of a semiconductor structure 100M according to another embodiment of the present disclosure;

FIG. 43 is a schematic diagram of a semiconductor structure 100N according to another embodiment of the present disclosure;

FIG. 44 is a schematic diagram of a semiconductor structure 100P according to another embodiment of the present disclosure;

FIG. 45 is a schematic diagram of a semiconductor structure 100Q according to another embodiment of the present disclosure; and

FIG. 46 is a schematic diagram of a semiconductor structure 100R according to another embodiment of the present disclosure.

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments could be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

This invention discloses methodologies, processes and structures to create the aforementioned full-sized composite wafers starting from a diamond substrate which is smaller than 8″ in diameter. What this invention achieves is at least: fill the large size gaps between diamond and silicon, between diamond and silicon-on-insulator (SOI), between diamond and silicon carbide (SiC) and between diamond and gallium nitride (GaN) through the creation of full-sized diamond based composite wafers (covering a diamond bi-wafer, a diamond tri-wafer and a diamond wafer) via heterogeneous integration of advanced packaging, wafer back-end-of-the-line (BEOL) and MEMS technologies. There also exist a large variety of other material combinations (including those for photonic, radio frequency (RF) and power devices) that can lead to the formation of composite wafers using the methodologies, processes and structures disclosed herein.

Although examples will be shown based primarily on the creation of diamond composite wafers for the fabrication of advanced ICs, advanced interposers and advanced multi-chip SiPs for HPC, data centers and AI applications, the invention disclosed herein can also be applied to other types of single-chip and multi-die packages for other applications as warranted including power electronics, passive devices, MEMS, nano-electromechanical systems (NEMSs), single crystal diamond (SCD) resonators, lasers and optics, silicon photonics, lateral high-mobility FETs (field effect transistors), vertical Schottky barrier diode devices, quantum memory, and (room-temperature) quantum computers.

For HPC, data center and AI applications, diamond enabled advanced ICs and advanced SiPs may be implemented in conjunction with both air cooling and liquid cooling (including direct-to-chip liquid cooling and liquid immersion cooling). Air cooling is running out of steam for very energy intensive data centers. Conventional air-cooled chips with finned metal heatsinks and small fans may support up to 400 W. High-performance chips generate far more heat with far higher heat densities than conventional chips, peaking in small hot spots inside them that may damage the delicate circuitry if not cooled properly. Liquid cooling with direct-to-chip liquid cooling in particular is already making inroads into data centers. Cooling with liquids, water included, could be 3-4 times more efficient than air cooling. Advanced cooling technologies like direct-to-chip liquid cooling using cold plates and direct liquid immersion cooling will play a key role in future hyperscale data center cooling as chip power continues to increase. Immersion cooling uses a leak-proof bath of dielectric fluid to submerge the full hardware. In both direct-to-chip cooling and immersion cooling, the liquid or fluid absorbs the heat, in some cases cools and condenses, and returns back as fluid to the bath.

The methodologies, processes and structures disclosed herein on the creation of diamond based composite wafers for the fabrication of diamond enabled advanced ICs, advanced interposers and advanced SiPs may be combined with new cooling methods such as direct-to-chip liquid cooling and liquid immersion cooling to maximize cooling effectiveness and efficiencies and to scale with rising chip power and liquid chip cooling trends.

Referring FIGS. 1A and 18 , FIG. 1A is a schematic diagram of a diamond composite wafer 100 according to an embodiment of the present disclosure, and FIG. 1B is a schematic diagram of a cross-sectional view of the diamond composite wafer 100 of FIG. 1A in a direction 1B-1B′. The diamond composite wafer 100 includes a plurality of diamond blocks 110 and a plurality of spacers 120 (such as filler including molding compound or silicon dioxide, SiO₂). Each spacer 120 fills a gap G1 between two adjacent diamond blocks 110. In another example, the spacers 120 may be connected as a continuous structure, as shown in FIG. 1A.

Each diamond block 110 is formed of, diamond. Diamond possesses a unique combination of extreme properties: (1) thermal conductivity (W/cm·K): up to about 24 for SCD vs. about 4 for copper, about 1.5 for silicon, about 3 for GaN and about 5 for SiC-4H; (2) breakdown field (MV/cm): about 20 vs. about 0.3 for silicon, about 5 for GaN and about 3 for SiC-4H; (3) electron mobility (cm²/Vs): about 4,500 vs. about 1,450 for silicon, about 440 for GaN and about 900 for SiC-4H; (4) hole mobility (cm²/Vs): about 3,800 vs. about 480 for silicon, about 200 for GaN and about 120 for SiC-4H; (5) band gap (eV): about 5.5 vs. about 3.44 for GaN and about 3.2 for SiC-4H; (6) broadband optical transparency: from about 230 nm to about 15 μm to about 1 mm; (7) coefficient of thermal expansion: about 0.7 ppm/° C.; (8) hardness (about 10 by Mohs, highest), wear resistance and chemically inertness.

Diamond has the highest thermal conductivity of any known material on Earth at temperatures above 100 K which is five times that of copper. Diamond also comes with high electrical resistivity (diamond can insulate high voltages across much thinner layers of material) and high electrical breakdown field. Diamond has a very low coefficient of thermal expansion. Semiconducting diamond's electronic band gap is bigger than silicon, and the two mainstream wide-band-gap materials, SiC and GaN for power electronics. Diamond is transparent from the UV (230 nm) to the far infrared. Only minor absorption bands exist between 2.5 and 6 μm (that result from two phonon absorption). Diamond is an ideal material for multispectral optical applications. Diamond is extremely hard, wear resistant and chemically inert. It is an ideal material for hostile, highly erosive atmospheres.

Single crystal diamond (SCD) is the ultimate material for high voltage, high temperature, and high frequency applications. For silicon-diamond composite wafers to be practical for HPC and other high-power applications, it is best that these wafers are to 12″ in diameter, the largest wafer size in mainstream IC fabrication and advanced SiP related wafer-level processes (including those for advanced interposers and fan-out packages) today, for productivity and cost reasons. By the same token, 8″ SiC-diamond composite wafers are preferred for SiC applications as SiC wafers are already available commercially in 8″.

Despite significant progress made in the recent past in growing larger, high-quality diamond wafers/plates, diamond can now be grown commercially to a size/diameter of about 145 mm in terms of polycrystalline diamond (PCD), and is available in the form of 50 mm×50 mm high-quality SCD plates, both up to 0.5 mm thick. These sizes are still much smaller than 12″, required by, for instance, 12″ silicon-diamond composite wafers, and smaller than 8″ required by, for instance, 8″ SiC-diamond composite wafers.

In addition, the diamond block 110 can be of the same size as the IC die (viewed from FIG. 1A), for example, 32 millimeter (mm)×26 mm for die, or of the same size as the interposer (viewed from FIG. 1A), for example, 40 mm×50 mm for interposer. In addition, the diamond block 110 (viewed from FIG. 1A) can assume a size of 2 inches×2 inches for SCD, or 5 inches×5 inches for PCD. Dicing or cutting of diamond plates to desired sizes can be achieved using a laser.

In an embodiment, the spacer 120 may be formed of a material including, for example, filler, molding compound, etc. Filler candidates include diamond, silicon dioxide (SiO₂), silicon nitride (Si₃N₄), spin-on-glass (SOG), and poly-silicon. The molding compound includes materials such as a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant, and may contain suitable fillers such as powdered SiO₂. The molding compound may be formed by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 1B, the spacer 120 has an upper surface 120 u, and the diamond block 110 has an upper surface 110 u, wherein the upper surface 110 u and the upper surface 120 u flush with each other.

FIG. 2 is a cross-sectional view of a schematic diagram of a diamond composite wafer 200 according to another embodiment of the present disclosure. The diamond composite wafer 200 includes a plurality of diamond blocks 110, a plurality of spacers 120 and a first semiconductor substrate 230. In the present embodiment, the diamond composite wafer 100 of FIG. 2 and the first semiconductor substrate 230 are connected to form the diamond composite wafer 200. A thermal conductivity of the first semiconductor substrate 230 is smaller than that of the diamond block 110.

As shown in FIG. 2 , each diamond block 110 has a dimension D1, and the first semiconductor substrate 230 has a predetermined diameter D2, wherein the dimension D1 is smaller than the predetermined diameter D2. The predetermined diameter D2 may be, for example, 12 inches, and the first semiconductor substrate 230 is silicon substrate, for example, silicon wafer. In another embodiment, the predetermined diameter D2 is 8 inches, and the first semiconductor substrate 230 is SiC substrate.

FIG. 3 is a schematic diagram of a cross-sectional view of a diamond composite wafer 300 according to another embodiment of the present disclosure. The diamond composite wafer 300 includes a plurality of diamond blocks 110, a plurality of spacers 120, the first semiconductor substrate 230 and a second semiconductor substrate 330. Each spacer 120 fills the gap G1 between two adjacent diamond blocks 110. In the present embodiment, the diamond composite wafer 200 of FIG. 2 and the second semiconductor substrate 330 are connected to form the diamond composite wafer 300.

The second semiconductor substrate 330 has the predetermined diameter D2. In the present embodiment, the predetermined diameter D2 may be, for example, 12 inches. The second semiconductor substrate 230 is silicon substrate, for example, silicon wafer. In another embodiment, the predetermined diameter D2 is 8 inches, and the second semiconductor substrate 330 is SiC substrate.

FIG. 4 is a schematic diagram of a cross-sectional view of a diamond composite wafer 400 according to another embodiment of the present disclosure. The diamond composite wafer 400 includes a plurality of the diamond blocks 110, a plurality of the spacers 120 and the second semiconductor substrate 330. Each spacer 120 fills the gap G1 between two adjacent diamond blocks 110. In the present embodiment, the diamond composite wafer 400 includes the features the same as or similar to that of the diamond composite wafer 300 except that, for example, the diamond composite wafer 400 may omit the first semiconductor substrate 230 of the diamond composite wafer 300.

FIG. 5 is a schematic diagram of a cross-sectional view of a diamond composite wafer 500 according to another embodiment of the present disclosure. The diamond composite wafer 500 includes a plurality of diamond blocks 110, a plurality of spacers 520 and a plurality of semiconductor blocks 531. Viewed from top of the diamond composite wafer 500, the spacers 520 may be connected as a continuous structure. The semiconductor block 531 may be obtained by cutting a Si wafer or a SiC wafer.

As shown in FIG. 5 , each spacer 520 fills the gap G1 between two adjacent diamond blocks 110 and a gap G2 between two adjacent semiconductor blocks 531. In an embodiment, the gap G1 may be equal to, greater than or smaller than the gap G2. The spacer 520 is formed of a material the same as or similar to that of the spacer 120. In addition, the diamond block 110 has the dimension D1 and the semiconductor block 531 has a dimension D3, wherein the dimension D3 of the semiconductor block 531 is smaller than, greater than or equal to the dimension D1 of the diamond block 110. The dimension D1 and the dimension D3 are smaller than the predetermined diameter D2. A thermal conductivity of the semiconductor block 531 may be smaller than that of the diamond block 110.

As shown in FIG. 5 , each spacer 520 has an upper surface 520 u, and the diamond block 110 has the upper surface 110 u, wherein the upper surface 110 u and the upper surface 520 u flush with each other.

FIG. 6 is a schematic diagram of a cross-sectional view of a diamond composite wafer 600 according to another embodiment of the present disclosure. The diamond composite wafer 600 includes the diamond composite wafer 500 and the second semiconductor substrate 330 attached to the diamond composite wafer 500. In the present embodiment, the diamond composite wafer 600 includes features the same as or similar to that of the diamond composite wafer 500 except that, for example, the diamond composite wafer 600 further includes the second semiconductor substrate 330 connected to the diamond composite wafer 500.

FIG. 7 is a schematic diagram of a cross-sectional view of a diamond composite wafer 700 according to another embodiment of the present disclosure. The diamond composite wafer 700 includes a plurality of diamond blocks 110, a plurality of spacers 520 and the second semiconductor substrate 330. In the present embodiment, the diamond composite wafer 700 includes the features the same as or similar to that of the diamond composite wafer 600 except that, for example, the diamond composite wafer 700 may omit the semiconductor blocks 531 and a portion of the spacer 520 within the gap G2 of FIG. 6 .

FIG. 8 is a schematic diagram of a cross-sectional view of a diamond composite wafer 800 according to another embodiment of the present disclosure. The diamond composite wafer 800 includes a plurality of composite blocks 800A and a plurality of spacers 520. Each composite block 800A includes a diamond layer 810 and the semiconductor block 531, wherein each diamond layer 810 is formed on the corresponding semiconductor block 531. Each spacer 520 fills the gap G1 between two adjacent diamond layers 810 and the gap G2 between two adjacent semiconductor blocks 531. In the present embodiment, the diamond block 810 may be formed using deposition, for example, chemical vapor deposition (CVD).

FIG. 9 is a schematic diagram of a cross-sectional view of a diamond composite wafer 900 according to another embodiment of the present disclosure. The diamond composite wafer 900 includes a plurality of diamond blocks 110, a plurality of spacers 520 and a plurality of silicon layers 831. Each silicon layer 831 is formed on the corresponding diamond block 110.

The silicon layer 831 may be a portion of a silicon-on-insulator (SOI) wafer. The SOI wafer includes a bulk silicon, a silicon dioxide (SiO₂) layer and a silicon layer 831, wherein the silicon dioxide layer is formed between the bulk silicon and the silicon layer 831. Before or after the SOI wafer is connected to the diamond block 110, the bulk silicon and the silicon dioxide layer may be removed. In an embodiment, the silicon layer 831 is a thin layer having a thickness ranging between around 100 nm to a few micrometers.

FIG. 10 is a schematic diagram of a cross-sectional view of a diamond composite wafer 1000 according to another embodiment of the present disclosure. The diamond composite wafer 900 includes a plurality of diamond blocks 110, a plurality of spacers 520, a plurality of silicon layers 831 and the second semiconductor substrate 330. In the present embodiment, the second semiconductor substrate 330 and the diamond composite wafer 900 of FIG. 9 are connected to each other.

FIG. 11 is a schematic diagram of a cross-sectional view of a diamond composite sub-assembly 1100 according to another embodiment of the present disclosure. The diamond composite sub-assembly 1100 includes one diamond block 110 and one semiconductor block 231 connected to the diamond block 110.

In another embodiment, the diamond composite wafer may include one diamond block 110 and one semiconductor block 831 of FIG. 9 connected to the diamond block 110, or include one diamond layer 810 of FIG. 8 and one semiconductor block 531 connected to the diamond layer 810, or include one diamond block 110 and one semiconductor block 531 of FIG. 6 connected to the diamond block 110.

FIG. 12 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer 1200 according to another embodiment of the present disclosure. The diamond composite IC wafer 1200 includes a diamond composite wafer 1101 and at least one first semiconductor substrate 1102. A plurality of the first semiconductor substrates 1102 are connected to each other by micro-bump or hybrid bonding, and the diamond composite wafer 1101 and at least one of the first semiconductor substrates 1102 are connected to each other. The diamond composite wafer 1101 includes the structure the same as or similar to that of the diamond composite wafer 100 of FIG. 1B. In the present embodiment, the first semiconductor wafer 1102 is, for example, an IC wafer which includes a set of IC circuits on a side of the first semiconductor wafer 1102.

FIG. 13 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer 1300 according to another embodiment of the present disclosure. The diamond composite IC wafer 1300 includes the diamond composite wafer 1101, at least one first semiconductor substrate 1102 and at least one diamond containing interposer 1203. A plurality of the first semiconductor substrates 1102 are connected to a plurality of the diamond containing interposers 1203. For example, one of the first semiconductor substrates 1102 is disposed between two adjacent diamond containing interposers 1203, or one of the diamond containing interposers 1203 is disposed between two adjacent first semiconductor substrates 1102. Although not shown, the diamond containing interposer 1203 may include a diamond layer, through diamond vias (TDVs) and a re-distribution layer (RDL) bonded to the diamond composite IC wafer 1200′, wherein the diamond composite IC wafer 1200′ includes the diamond composite wafer 1101 and at least one first semiconductor substrates 1102.

FIG. 14 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer 1400 according to another embodiment of the present disclosure. The diamond composite IC wafer 1400 includes a diamond wafer 1301 and at least one first semiconductor substrate 1102. A plurality of the first semiconductor substrates 1102 are connected to each other, and the diamond wafer 1301 and one of the first semiconductor substrates 1102 are connected to each other.

FIG. 15 is a schematic diagram of a cross-sectional view of a diamond composite IC wafer 1500 according to another embodiment of the present disclosure. The second diamond composite IC wafer 1500 includes the diamond wafer 1301, at least one first semiconductor substrate 1102 and at least one diamond interposer 1203. A plurality of the first semiconductor substrates 1102 are connected to a plurality of diamond containing interposers 1203. For example, one of the first semiconductor substrates 1102 is disposed between two adjacent diamond containing interposers 1203, or one of the diamond containing interposers 1203 is disposed between two adjacent first semiconductor substrates 1102. Although not shown, the diamond containing interposer 1203 may include a diamond layer, TDVs and a re-distribution layer (RDL) bonded to the diamond composite IC wafer 1400′, wherein the first diamond composite IC wafer 1400′ includes the diamond wafer 1301 and at least one first semiconductor substrates 1102.

As described above, using a full-sized diamond wafer (for example, the diamond composite wafer 100 of FIG. 1B), a diamond bi-wafer (for example, the diamond composite wafer 200 of FIG. 2 ), a diamond tri-wafer (for example, the diamond composite wafer 300 of FIG. 3 ), one may proceed to build complex micro-machined advanced ICs and advanced interposers with redistribution layers (RDL) on both sides (front side, or chip/circuitry side, and backside) of the wafers and metal filled through-diamond vias (TDVs) or through-silicon/diamond-vias (TSDVs). Metal here can be Cu, W, Co, Mo, etc.

To facilitate seamless advanced IC fabrication and advanced package processing, the overall thickness of the diamond bi-wafer or the diamond tri-wafer, in one example, could be equal to (but not limited to) the thickness of a standard 12″ silicon wafer which is about 775 μm or the thickness (˜500 μm) of 8″ SiC wafers. The diamond tri-wafer may be used for making thin or ultrathin ICs such as high-end processors, or high-bandwidth-memory DRAM (which can be as thin as 30 μm), while the diamond bi-wafer (and even the diamond tri-wafer depending on desired final IC thicknesses and cooling requirements) may be used for processor ICs and 2.5D interposers. When tri-wafers are employed for the fabrication of thin ICs, the combined thickness of a silicon layer and the diamond layer in the tri-wafer preferably should be equal to the final IC thickness with removal of the second silicon layer (which serves as the carrier or support to ensure structural integrity during thin IC processing) prior to the end of processing.

FIGS. 16A to 16F are schematic diagrams of manufacturing processes of the diamond composite wafer 200 of FIG. 2 according to an embodiment of the present disclosure.

As shown in FIG. 16A, a plurality of diamond blocks 110 are prepared, wherein each diamond block 110 has the dimension D1 smaller than the predetermined diameter D2 as shown in FIGS. 16B and 16C. The diamond blocks 110 are bonded to a temporary carrier 10 as shown in FIG. 16B.

As shown in FIGS. 16B to 16D, the diamond blocks 110 are attached to the first semiconductor substrate 230 (as shown in FIG. 16C) with the predetermined diameter D2 to form a temporary composite wafer 200′ (as shown in FIG. 16D), wherein a thermal conductivity of the first semiconductor substrate 230 is smaller than that of each diamond block 110.

Furthermore, as shown in FIG. 16B, the diamond blocks 110 are attached on the temporary carrier 10 with the predetermined diameter D2 by a release layer 20. Then, as shown in FIG. 16C, the diamond blocks 110 which are attached to the temporary carrier 10 are bonded to the first semiconductor substrate 230. Then, as shown in FIG. 16D, the temporary carrier 10 and the release layer 20 are removed from the diamond blocks 110 to expose the diamond blocks 110 and to form the temporary composite wafer 200′. In an embodiment, the predetermined diameter D2 may be, for example, 12 inches, and the first semiconductor substrate 230 is silicon substrate, for example, silicon wafer. In another embodiment, the predetermined diameter D2 is 8 inches, and the first semiconductor substrate 230 is SiC substrate.

In an embodiment, before bonding the diamond blocks 110 to the first semiconductor substrate 230, the surfaces of the diamond blocks 110 and the surface of the first semiconductor substrate 230 preferably should have a arithmetic average roughness, Ra (arithmetic average roughness, or RMS, root mean square average roughness) smaller than 1 nm which is achievable by chemical mechanical polishing (CMP) and be treated, for example, by surface pre-conditioning and activation prior to bonding. The treated surfaces of the diamond blocks 110 are bonded to the treated surface of the first semiconductor substrate 230 with a glue layer 240 (as shown in FIG. 16C) or without the glue 240.

Pre-bonding conditioning of diamond and silicon surfaces can involve

-   -   Chemical mechanical polish (CMP) to achieve, preferably a         surface roughness, Ra (arithmetic average roughness, or RMS,         root mean square average roughness)<1 nm for both diamond and         silicon. This level of Ra can be achieved by CMP for silicon and         SCD, and by a combination of sacrificial SiO₂ layer deposition,         and SiO₂ planarization by CMP and deep reactive ion etching         (DRIE) for PCD (and SCD as needed)—when needed, deep reactive         ion etching (DRIE) can be employed in to help achieve Ra<1 nm,     -   Wet surface pre-treatments involving ultrasonic de-ionized (DI)         water clean, H₂SO₄/H₂O₂ treatment, NH₃/H₂O₂ treatment, and N₂         blow dry,     -   Plasma/inductively coupled plasma reactive ion etching         (ICP-RIE): O₂, N₂, H₂/O₂,     -   Deep RIE (DRIE): O₂/CF₄, and     -   Activation of the bonding surfaces (with and/or without the glue         layers) inside bonding machines prior to bonding by a fast atom         beam gun, FAB (using, for instance, argon neutral atom beam at         ˜1 keV), or by an ion gun (using for instance, argon ion at ˜60         eV) to remove oxide films in vacuum and to reveal dangling bonds         at the surfaces for bonding.     -   (Note: FAB works well for (sputtered) Si/Si, Si/SiO₂, metals,         compound semiconductors and single crystal oxides, while ion         guns are known to work for SiO₂/SiO₂, Glass, Si₃N₄ (silicon         nitride)/Si₃N₄, Si/Si, Si/SiO₂, metals, compound semiconductor,         and single crystal oxides. A vacuum of 10⁻⁶ Pa (pascal) is         preferred during bonding to prevent re-adsorption to activated         bonding surfaces.)

The glue layer 240, which can be an electrical insulator or an electrical conductor, may be selected from the group consisting of Si (e.g., poly-silicon), SiO₂, Si₃N₄, Al₂O₃ (alumina), diamond, boron nitride, aluminum nitride and graphene; or selected from the group consisting of Ti, W, Pt, Cr, Au, Cu, Ir, nickel (Ni), nickel-vanadium (Ni—V), iron (Fe), Ag—In, Au—In, Ag, Sn, Mo and other types of transient liquid phase bonding metals; or selected from the group consisting of Ir on SrTiO₃, Ir on YSZ/Si, Ir on MgO, and sapphire or TaO₃, or combinations thereof. When coating on the backside of an active IC wafer involves the use of an electrically conductive glue layer, a diffusion barrier (and also adhesion) layer, for example, can be deposited on the wafer backside first. This barrier layer can be Ti, chromium (Cr) or tungsten (W). A stack of Ti, Ti/nickel-vanadium (Ni—V) and Ag can also be sputter deposited on Si backside following in-situ sputter etching using argon (Ar) to remove native oxides from the Si backside to prepare the Si for bonding where the Ti layer can serve as the barrier to Ni diffusion towards Si, and the Ni—V layer, a solderable intermediate layer, forms good bonds with soft solders, and the bonding Ag layer protects the underlying layers from oxidation and enables solderability.

The Ti/Ni-V/Ag metal stack can be tailored to achieve low stresses and low wafer warpage which is particularly important for thin ICs commonly found in 3D IC structures by adjusting sputtering conditions. Ag to Ag and Au to Au bonding using a thermal compression bonder (TCB) can take place at temperatures below 250° C. Ag and Au have high thermal conductivities at 430 W/m·K, and 320 W/m·K, respectively (versus ˜400 W/m·K for copper and 148 W/m·K for silicon) and high melting points at 961° C. and 1064° C., respectively. Au is more costly compared to Ag. Ag and Au can be sputter deposited or plated. Ag can also be sintered Ag.

As shown in FIG. 16E, a plurality of the gaps G1 among the diamond blocks 110 of the temporary composite wafer 200′ are filled with spacer material 120′. The spacer material 120′ may be formed of a material including, for example, filler, molding compound, etc. The filler can be diamond, silicon dioxide (SiO₂), silicon nitride (Si₃N₄), spin-on-glass (SOG), poly-silicon, etc., and the filler can be formed using deposition (e.g., CVD), spin coating etc. The molding compound can include a material such as a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant with suitable fillers such as powdered SiO₂. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 16F, a portion of the spacer material 120′ is removed to form a plurality of the spacer 120 by using, for example, chemical mechanical polishing (CMP), deep reactive ion etching (DRIE), etc. Furthermore, the spacer material 120′ can be planarized to expose the diamond blocks 110 to form the diamond composite wafer 200. After planarization, the spacers 120 each having the upper surface 120 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surfaces 110 u and the upper surfaces 120 u flush with each other. Each of the spacers 120 fills the gap G1 between two adjacent diamond blocks 110. So far, the diamond composite wafer 200 of FIG. 2 is formed or completed.

In another embodiment, the first semiconductor substrate 230 of the diamond composite wafer 200 of FIG. 16F may be removed to form the diamond composite wafer 100 of FIG. 1B.

In other embodiment, the second semiconductor substrate 330 of FIG. 3 may be attached to the diamond blocks 110 of FIG. 16F to form the diamond composite wafer 300 of FIG. 3 .

In other embodiment, the first semiconductor substrate 230 of the diamond composite wafer 300 of FIG. 3 may be removed to form the diamond composite wafer 400 of FIG. 4 .

FIGS. 17A to 17D are schematic diagrams of manufacturing processes of the diamond composite wafer 500 of FIG. 5 according to an embodiment of the present disclosure.

As shown in FIG. 17A, a plurality of the diamond blocks 110 and a plurality of the semiconductor blocks 531 are attached to a temporary carrier 10A with the predetermined diameter D2 to form a temporary composite wafer 500′. The diamond block 110 has the dimension D1 and the semiconductor block 531 has the dimension D3, wherein the dimension D1 and the dimension D3 are smaller than the predetermined diameter D2. In addition, a thermal conductivity of the semiconductor block 531 is smaller than that of the diamond block 110.

Two adjacent diamond blocks 110 are spaced by the gap G1, and two adjacent semiconductor blocks 531 are spaced by the gap G2. In an embodiment, the gap G1 may be equal to, greater than or smaller than the gap G2.

In an embodiment, before the diamond blocks 110 and the semiconductor blocks 531 are bonded to the temporary carrier 10A with a release layer 20, the surfaces of the diamond blocks 110 and the surfaces of the semiconductor blocks 531 may be pre-treated and activated. The treated surfaces of the diamond blocks 110 are bonded to the treated surface of the semiconductor blocks 531 with the glue layer 240 (not shown in FIG. 17 ; see FIG. 16C) or without the glue layer 240. In addition, the release layer 20 may be removed along with the temporary carrier 10A. When coating on the backside of an active IC wafer is involved, a diffusion barrier layer, for example, can be deposited on the wafer backside first. This barrier layer can be Ti, chromium (Cr), tungsten (W) or other aforementioned materials and material combinations.

As shown in FIG. 17B, the gaps G1 between diamond blocks 110 and the gaps G2 between semiconductor blocks 531 are filled with the spacer material 520′.

The spacer material 520′ may be formed of a material including, for example, filler, molding compound, etc. The filler candidate can include diamond, silicon dioxide (SiO₂), silicon nitride (Si₃N₄), spin-on-glass (SOG), poly-silicon, etc., and the filler is formed using deposition, spin coating, etc. The molding compound includes a material such as a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant, and suitable fillers such as powdered SiO₂. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 17C, a portion of the spacer material 520′ is removed to form a plurality of the spacer 520 by using, for example, CMP, DRIE, etc. Each of the spacers 520 fills the gap G1 between two adjacent diamond blocks 110 and the gap G2 between two adjacent semiconductor blocks 531. Furthermore, the spacer material 520′ is planarized to expose the diamond blocks 110. After planarization, the spacers 520 each having the upper surface 520 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surface 110 u and the upper surface 520 u flush with each other.

As shown in FIG. 17D, the temporary carrier 10A and the release layer 20 are removed to expose the semiconductor blocks 531 and to form the diamond composite wafer 500.

In another embodiment, the diamond composite wafer 500 of FIG. 17D and the second semiconductor substrate 330 are connected to each other to form the diamond composite wafer 600 of FIG. 6 .

In another embodiment, the diamond composite wafer 500 of FIG. 17D and the first semiconductor substrate 230 are connected to each other.

In another embodiment, the semiconductor blocks 531 and a portion of each spacer 520 (see FIG. 17D) are removed from the diamond composite wafer 600 of FIG. 6 to form the diamond composite wafer 700 of FIG. 7 .

In another embodiment, the semiconductor blocks 531 and a portion of each spacer 520 of FIG. 17D are removed to form the diamond composite wafer 100 of FIG. 1B.

In another embodiment, the semiconductor blocks 531 and the diamond blocks 110 of FIG. 17A may be replaced by a plurality of the composite blocks 800A of FIG. 8 . Furthermore, the composite block 800A may be formed by depositing the diamond layer 810 on the semiconductor blocks 531, followed by the deposition of a sacrificial layer such as CVD silicon dioxide on the diamond layer 810, and planarization and etching of the sacrificial layer through a combination of CMP and DRIE to form the composite block 800A, wherein each composite block 800A includes the diamond layer 810 on the semiconductor block 531. Then, the composite blocks 800A are attached on the temporary carrier 10A by the release layer 20. The other process steps of the diamond composite wafer 800 of FIG. 8 are the same as or similar to the corresponding process steps of the diamond composite wafer 500, and the similarities will not be repeated here.

FIGS. 18A to 18F are schematic diagrams of manufacturing processes of the diamond composite wafer 500 of FIG. 5 according to another embodiment of the present disclosure.

As shown in FIG. 18A, the diamond blocks 110 are attached on a temporary carrier 10B with the predetermined diameter D2 by the release layer 20. Two adjacent diamond blocks 110 are spaced by the gap G1.

As shown in FIG. 18B, the semiconductor blocks 531 are attached on a temporary carrier 10C with the predetermined diameter D2 by the release layer 20 (or a release layer different from that used to bond the diamond blocks 110 to the temporary carrier 10B). Two adjacent semiconductor block 531 are separated by the gap G2.

As shown in FIG. 18C, the diamond blocks 110 which are attached to the temporary carrier 10B are bonded to the semiconductor blocks 531 which are attached to the temporary carrier 10C with or without the glue layer 240.

In an embodiment, before the diamond blocks 110 are bonded to the semiconductor blocks 531, the surfaces of the diamond blocks 110 and the surfaces of the semiconductor blocks 531 may be pre-treated and activated. The treated surfaces of the diamond blocks 110 are bonded to the treated surface of the semiconductor blocks 531 with the glue layer 240 or without the glue 240. In addition, the release layer 20 may be removed with the temporary carrier 10B to reveal the diamond blocks 110 on the semiconductor blocks 531. When coating on the backside of an active IC wafer is involved, a diffusion barrier layer, for example, can be deposited on the wafer backside first. This barrier layer can be Ti, chromium (Cr), tungsten (W) or other aforementioned materials and material combinations.

As shown in FIG. 18D, the temporary carrier 10B is removed to expose the diamond blocks 110.

As shown in FIG. 18E, the gaps G1 among the diamond blocks 110 and the gaps G2 among the semiconductor blocks 531 are filled with the spacer material 520′. The spacer material 520′ may be formed of a material including, for example, filler, molding compound, etc. The filler can be formed using deposition, spin coating, etc. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 18F, a portion of the spacer material 520′ is removed to form the spacers 520 by using, for example, CMP, DRIE, etc. Furthermore, the spacer material 520′ is planarized to expose the diamond blocks 110. After planarization, the spacers 520 each having the upper surface 520 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surface 110 u and the upper surface 520 u flush with each other.

Then, the temporary carrier 10C and the release layer 20 of FIG. 18F b are removed to form the diamond composite wafer 500 of FIG. 5 .

FIGS. 19A to 19E are schematic diagrams of manufacturing processes of the diamond composite wafer 900 of FIG. 9 according to an embodiment of the present disclosure.

As shown in FIG. 19A, the diamond block 110 is attached to the semiconductor block 831, wherein each semiconductor block 831 is a SOI block with the Si layer 8311, the SiO₂ layer 8312 and the Si bulk 8313, and the SiO₂ layer 8312 is formed between the Si layer 8311 and the Si bulk 8313.

The surfaces of the diamond blocks 110 and the surfaces of the semiconductor blocks 831 may be pre-treated and activated. The treated surfaces of the diamond blocks 110 on a temporary carrier (not shown) are bonded to the treated surface of the semiconductor blocks 831 on another temporary carrier (not shown) with the glue layer 240 or without the glue layer 240. Following bonding, the temporary carrier supporting the semiconductor block is released along with the release layer, followed by removal of the Si bulk 8313 and the SiO₂ layer 8312. This is then followed by bonding of the third temporary carrier to the exposed Si layers 8311 bonded to the diamond blocks, and removal of the temporary carrier supporting diamond blocks leading to the structure shown in FIG. 19C.

As shown in FIG. 19B, the Si bulk 8313 is removed by using, for example, back-grinding, CMP, a KOH etch, etc., and the SiO₂ layer 8312 is removed by using, for example, HF etch, etc. The silicon oxide layer may be etched off with a HF etching step. For silicon, common chemical etchants are mixtures of nitric acid (HNO₃) and hydrofluoric acid (HF). One of the most common etchant used to remove SiO₂ is dilute solutions of HF. After the Si bulk 8313 and the SiO₂ layer 8312 are removed, the Si layer 8311 is exposed and the diamond block 110 and the Si layer 8311 form one composite block 900A supported by the third temporary carrier 10B.

SOI enables lower overall processor operating powers. Compared to bulk silicon, ICs built by SOI wafers show a performance gain of 30% at identical feature sizes due to the electrical isolation provided by SiO₂. Replacing SiO₂ with diamond with a thermal conductivity (TC) that is over 2000 times that of SiO₂ may dramatically improves processor performance and enables 10× powers and 3× circuit densities compared to SOIs based on SiO₂.

Bonding of SCD to SiC may be achieved at room (or low temperatures) by protecting the diamond surface with an ultrathin metal layer such as Ti of 10 nm or less during FAB (using, e.g., Ar neutral atom) irradiation (i.e., surface activation) prior to SiC-to-diamond bonding. There are many applications that may take advantage of SiC-diamond bonding for enhanced heat dissipation, two of which are high-power GaN HEMT to boost radar performance and cooling of SiC devices for high-power, high-temperature and high-reliability applications such as SiC inverters for electrical vehicles. GaN is a material that may be used in the production of semiconductor power devices, LEDs and RF components. GaN may be integrated with diamond to boost its performance using the processes and structures disclosed above. GaN on diamond makes the material particularly attractive for high power RF applications such as radar applications. GaN based HEMTs are suitable for microwave and millimeter-wave amplifiers with high output power and high-efficiency in long distance radio wave applications. During their operation in high speed switching applications, the local flux value could reach more than ten times larger than that of the sun surface. Proper heat spreading by placing diamond as close as possible to the hot spots (and better yet to immediate vicinity of chip hot spots) may decrease the channel temperature effectively, facilitating device stability and use life. SiC is currently used as the substrate in some GaN HEMT power amp applications to facilitate heat dissipation. Even though the TC of SiC is already high, diamond with a far higher TC than SiC (about 4-5×) may be bonded to SiC and the two combined also allow increasing power output and hence GaN HEMT increased performance.

As shown in FIG. 19C, a plurality of the composite blocks 900A of FIG. 19B are attached on the temporary carrier 10B using the release layer 20.

As shown in FIG. 19D, the gaps G1 between diamond blocks 110 and the gaps G2 between Si layers 8311 are filled with the spacer material 520′. The spacer material 520′ may be formed of a material including, for example, filler, molding compound, etc. The filler is formed using deposition, spin coating, etc. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 19E, a portion of the spacer material 520′ is removed to form a plurality of the spacer 520 by using, for example, CMP, DRIE, etc. Each of the spacers 520 fills the gap G1 between two adjacent diamond blocks 110 and the gap G2 between two adjacent Si layers 8311. Furthermore, the spacer material 520′ is planarized to expose the diamond blocks 110. After planarization, the spacers 520 each having the upper surface 520 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surface 110 u and the upper surface 520 u flush with each other.

Then, the temporary carrier 10B and the release layer 20 of FIG. 19E are removed to form the diamond composite wafer 900 of FIG. 9 .

In an embodiment, a second semiconductor substrate 330 is attached to the diamond blocks 110 and the temporary carrier 10B and the release layer 20 of FIG. 19E are removed to form the diamond composite wafer 1000 of FIG. 10 .

In another embodiment, a new temporary carrier (not shown) is attached to the structure in FIG. 19E to the surface with exposed diamond and then the temporary carrier 10B and the release layer 20 of FIG. 19E are removed. This is then followed by the removal of the Si layers 8311 and a portion of the spacer 520 to form the diamond composite wafer 100 of FIG. 1B.

FIGS. 20A to 20J are schematic diagrams of manufacturing processes of the diamond composite wafer 900 of FIG. 9 according to another embodiment of the present disclosure.

As shown in FIG. 20A, the diamond blocks 110 are attached on the temporary carrier 10B with the predetermined diameter D2. Each diamond block 110 has the dimension D1 smaller than the predetermined diameter D2 of the temporary carrier 10B.

As shown in FIG. 20B, the semiconductor blocks 831 are attached on the temporary carrier 10C with the predetermined diameter D2, wherein each semiconductor block 831 is the SOI block with the Si layer 8311, the SiO₂ layer 8312 and the Si bulk 8313, and the SiO₂ layer 8312 is formed between the Si layer 8311 and the Si bulk 8313. Each semiconductor block 831 has the dimension D3 equal to, smaller than or greater than the dimension D1 of the diamond block 110 of FIG. 20A.

As shown in FIG. 20C, the diamond blocks 110 which are attached to the temporary carrier 10B are attached to the semiconductor blocks 831 which are attached to the temporary carrier 10C.

Before the diamond blocks 110 are bonded to the semiconductor blocks 831, the surfaces of the diamond blocks 110 and the surfaces of the semiconductor blocks 831 may be pre-treated and activated. The treated surfaces of the diamond blocks 110 are bonded to the treated surface of the semiconductor blocks 831 with the glue layer 240 or without the glue layer 240.

As shown in FIG. 20D, the temporary carrier 10C is removed to reveal the semiconductor block 831.

As shown in FIG. 20E, the Si bulk 8313 is removed by using, for example, back-grinding, CMP, a KOH etch, etc., and the SiO₂ layer 8312 is removed by using, for example, HF etch, etc. After the Si bulk 8313 and the SiO₂ layer 8312 are removed, the Si layer 8311 is exposed and the diamond block 110 and the Si layer 8311 form one composite block 900A.

As shown in FIG. 20F, the temporary carrier 10A is attached to the revealed Si layers 8311 with the release layer 20.

As shown in FIG. 20G, the temporary carrier 10B and the release layer 20 of FIG. 20F are removed to expose the diamond blocks 110.

As shown in FIG. 20H, the gaps G1 between diamond blocks 110 and the gaps G2 between semiconductor blocks 531 are filled with the spacer material 520′. The spacer material 520′ may be formed of a material including, for example, filler, molding compound, etc. The filler is formed through deposition, coating, molding etc. of a material such as a molding compound, a spin-on glass (SOG), diamond, SiO₂, polysilicon, etc. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 20I, a portion of the spacer material 520′ is removed to form a plurality of the spacers 520 by using, for example, CMP, DRIE, etc. Each of the spacers 520 fills the gap G1 between two adjacent diamond blocks 110 and the gap G2 between two adjacent Si layers 8311. Furthermore, the spacer material 520′ is planarized to expose the diamond blocks 110. After planarization, the spacers 520 each having the upper surface 520 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surface 110 u and the upper surface 520 u flush with each other.

As shown in FIG. 20J, the second semiconductor substrate 330 is attached to the diamond blocks 110. In another embodiment, the first semiconductor substrate 230 may be attached to the diamond blocks 110.

Then, the temporary carrier 10A and the release layer 20 of FIG. 20J are removed to expose the Si layers 8311 and form the diamond composite wafer 1000 of FIG. 10 .

In an embodiment, the temporary carrier 10A and the release layer 20 of FIG. 20I are removed to form the diamond composite wafer 900 of FIG. 9 .

As described above, a filler material such as diamond or SiO₂ is deposited by CVD. Molding compound is overmolded on diamond plates by transfer or compression molding machines. When diamond is used as the filler, it may be planarized following filler deposition to form 12″ silicon-diamond bi-wafer with the use of a combination of sacrificial layer such as CVD SiO₂ (after diamond deposition and some preliminary CMP) deposition, CMP and DRIE. In the case of molding compound, it may be planarized by backgrinding, as is typical of fan-out processing. Poly-silicon may be deposited using catalytic CVD at a temperature as low as 180° C. SiO₂, on the other hand, may be deposited at 250° C. by plasma enhanced CVD. SOG which mixes SiO₂ and either boron or phosphorous with the mixture suspended in a solvent solution. It is easy to apply by spin coating it onto a particle-free substrate. SOG may achieve good thickness uniformity. Siloxane type SOG may be deposited by multiple spin, bake and cure processes.

FIGS. 21A to 21C are schematic diagrams of manufacturing processes of the diamond composite IC wafer 1200 of FIG. 12 according to an embodiment of the present disclosure.

As shown in FIG. 21A, the first semiconductor wafer 1102 with the predetermined diameter D2 are prepared, wherein the first semiconductor wafer 1102 includes a set of IC circuits on a first side of the first semiconductor wafer 1102.

As shown in FIG. 21B, the diamond composite wafer 1101 with the predetermined diameter D2 is prepared.

As shown in FIG. 21C, the diamond composite wafer 1101 is bonded to the first semiconductor wafer 1102 to form the diamond composite IC wafer 1200′.

Then, at least one first semiconductor wafers 1102 is attached to the diamond composite wafer of the diamond composite IC wafer 1200′ of FIG. 21C to form the diamond composite IC wafer 1200 of FIG. 12 , and a plurality of the first semiconductor wafers 1102 can be connected to the diamond composite IC wafer 1200′ by micro-bump or copper hybrid bonding.

In another embodiment, at least one diamond containing interposer 1203 and at least one first semiconductor wafers 1102 of FIG. 13 may be bonded to the diamond composite IC wafer 1200′ of FIG. 21C to form the diamond composite IC wafer 1300 of FIG. 13 .

The diamond composite IC wafer is bonded to the semiconductor wafer through, for example, micro-bump, or copper hybrid bonding based on oxide-to-oxide bonding or polyimide (PI)-to-PI bonding. Furthermore, when copper hybrid bonding instead of the traditional micro-bumps is used for interconnection, the packages may be leak-proof in the case of immersion cooling (when a dielectric coolant is used) using oxide-to-oxide based copper hybrid bonding. For copper hybrid bonding, one may choose oxide-to-oxide bonding or polyimide (PI)-to-PI bonding for bonding two IC wafers, an IC wafer and an interposer wafer, or a diamond wafer and an IC wafer using silicon dioxide (SiO₂) or PI as the BEOL dielectric/bonding layers.

Direct oxide-to-oxide bonding proceeds generally in the following process sequence: (1) formation of dangling bonds and bonding between hydroxyl groups and water molecules through plasma activation using gases such as O₂ (oxygen)/N₂ (nitrogen)/Ar (argon); (2) removal of defects through deionized water cleaning and scrubbing; (3) bonding of wafers (or wafer and wafer-sized interposer) with oxide bonding layers at room temperature and atmospheric pressure via van der Waals hydrogen bonds between two to three monolayers of water molecules and polar hydroxyl (OH) groups (which terminate at both the native and thermal SiO₂); (4) formation of van der Waals bonds between H₂O molecules and silanol groups (Si—OH—(H₂O)x-HO—Si; silanol group ═Si—OH) on the top and bottom wafer surfaces; and (5) annealing to remove water molecules at the interface and form covalent bonds at temperatures typically less than 400° C. Void formation caused by water droplet formation (the Joule-Thomason expansion effect) at wafer edge during direct bonding must be avoided by controlling key parameters such as plasma conditions, surface roughness, degree of cleanliness, wafer warpage/flatness and bonding conditions. In the case of oxide-to-oxide bonding, one may also vary oxide type and deposition technique, process conditions such as plasma gas, plasma power, surface roughness pertaining to chemical mechanical polish (CMP), surface cleanliness, mono- to multiple layers of water molecules from de-ionized cleaning, bonding conditions (such as temperature and speed), and anneal conditions (e.g., anneal temperatures, anneal time and number of annealing steps) to maximize the bonding yield and shear strength between two wafers.

Regarding PI-to-PI bonding using fully cured polyimide-to-fully cured polyimide bonding based on pyromellitic dianhydride (PMDA) and 4,4′-diaminodiphenyl ether (4,4′-ODA) as an example, one may maximize the shear strength by varying conditions such as volume of water introduced, bonding time, and oxygen (O₂) plasma activation time. To achieve void-free PI-to-PI bonding, it is important to activate the PI surfaces by oxygen plasma activation to generate low-density hydrophilic groups on the PI surface which effectively enhances adsorption of water molecules introduced by a de-ionized water wetting process. The adsorbed water molecules, in turn, brings in considerable high-density OH (hydroxyl) groups which facilitate pre-bonding Following PI surface activation and wetting, PI-to-PI hybrid bonding may take place at a relative low temperature of 250° C. for a few minutes only when a permanent bond is desired. Neither the plasma process nor the wetting or hydration process alone may achieve good bonding. Key parameters to manipulate in order to achieve good bond yield include plasma activation time, volume of water introduced, bonding temperature and bonding time.

Oxide-to-oxide hybrid bonding requires high component flatness and surface cleanliness to avoid electrical interconnection fails due to silicon dioxide's high hardness and poor deformation characteristics. Compared to the conventional oxide-to-oxide hybrid bonding, PI-to-PI bonding which may require application of an external pressure during bonding allows for higher surface roughness and is more tolerant of component flatness due to the low modulus and more compliant characteristics of the PIs.

The explosion in data is driving extraordinary growth in internet traffic and cloud services. Silicon photonics will take the center stage in defining new mega data center architectures in order to manage the unabated growth in data traffic. New microelectronics packaging technologies are required to address optical-to-electrical interconnection as photon and electron exchanges move from optical transceivers mounted at the edge of server boards (in server racks inside mega data centers) to IC packages and logic chips inside these computing systems. Optics has traditionally been deployed to transmit data over long distances because light may carry considerably more information content (bits) at faster speed and light is more energy efficient compared to electronic alternatives to transmit data when the transmission length and bandwidth increases. Optical transceivers represent the initial high volume application for silicon photonics starting from 100 G as optics migrates as close as possible to the source of the data, resulting in large distances between the optical components and the processor chip. Using the silicon interposer based optical module as an example, its performance may be greatly enhanced by replacing the silicon interposer with a silicon-diamond bi-wafer interposer containing backside power supply and both optical waveguides and active and passive functions in silicon. Using a combination of photolithography, reactive ion etching (RIE) and focused ion beam techniques, one may also fabricate in the diamond portion of the bi-wafer an optical chip that integrates function elements such as X-crossings, Y-functions, evanescent couplers, Bragg reflectors/couplers and various interferometers. As the need for higher data transfer speeds at greater baud rates and lower power levels intensifies, the trend is for optics to be moved even closer to the die. To this end, optoelectronic interconnect will need to be designed to interface directly to the processor, whether it be application specific integrated circuit (ASIC) or FPGA, to support switching, transceiver, signal conditioning and multiplexer/demultiplexer applications. This requires co-packaging of the optical module based on a silicon interposer with processor such as silicon based ASIC/FPGA/CPU (or its chiplets) flip chip bonded to a laminate substrate. As in the case of silicon-diamond bi-wafer enhanced optical module, the performance of this more complex SiP may be greatly enhanced by mounting the bi-wafer enabled optical module and the bi-wafer enabled ASIC/FPGA/CPU (with a diamond heat spreader attached) on a diamond or silicon-diamond interposer as shown by a bottom structure.

FIGS. 22A to 22C are schematic diagrams of manufacturing processes of the diamond composite IC wafer 1200 of FIG. 12 according to another embodiment of the present disclosure.

As shown in FIG. 22A, the first semiconductor wafer 1102 with the predetermined diameter D2 are prepared, wherein the first semiconductor wafer 1102 includes a set of IC circuits on a first side of the first semiconductor wafer 1102. Then, a plurality of the diamond blocks 110 each having the dimension D1 are prepared, and then are attached on the first semiconductor wafer 1102.

Before bonding, it can be advantageous that diamond is deposited with a surface layer that forms chemical bonds with diamond such as Ti or W, and a bonding layer such as Au or a solder (or a transient liquid phase material), and the backside of silicon deposited with a good diffusion barrier layer such as Ti, TiN, Ti/TiN or Ti/Ni and a bonding layer such as Au or a solder to enable low-temperature bonding at temperatures preferably below 300° C. In addition, the diffusion barrier layer may be formed on a second side of the first semiconductor wafer 1102.

As shown in FIG. 22B, a plurality of the gap G1 among the diamond blocks 110 are filled with spacer material 120′.

The spacer material 120′ may be formed of a material including, for example, filler, molding compound, etc. The filler can be diamond, silicon dioxide (SiO₂), silicon nitride (SiN₄), spin-on-glass (SOG), polysilicon, etc., and the filler is formed using deposition, spin coating, molding, etc. The molding compound includes a material, for example, a Novolac-based resin, an epoxy-based resin, a silicone-based resin, or another suitable encapsulant, and suitable fillers such as powdered SiO₂. The molding compound may be overmolded on the diamond blocks 110 by using, for example, transfer molding, compression molding, etc.

As shown in FIG. 22C, a portion of the spacer material 120′ is removed to form a plurality of the spacer 120 by using, for example, CMP, DRIE, etc. Each the spacer 120 fills the gap G1 between two adjacent diamond blocks 110. Furthermore, the spacer material 120′ may be planarized to expose the diamond blocks 110 to form the diamond composite wafer 200. After planarization, the spacers 120 each having the upper surface 120 u and the diamond blocks 110 each having the upper surface 110 u are formed, and the upper surfaces 110 u and the upper surfaces 120 u flush with each other. After planarization, the first semiconductor wafer 1102, the spacers 120 and the diamond blocks 110 form the diamond composite IC wafer 1200′ of FIG. 13 .

Then, at least one first semiconductor wafers 1102 is bonded with diamond blocks to form the diamond composite IC wafer 1200 of FIG. 12 (or the diamond composite IC wafer 1200′ of FIG. 22C), and a plurality of the first semiconductor wafers 1102 can be connected to the diamond composite IC wafer 1200′ and the interposers by micro-bump or copper hybrid bonding.

In another embodiment, at least one diamond containing interposer 1203 and at least one first semiconductor wafers 1102 of FIG. 13 may be bonded to the diamond composite IC wafer 1200′ of FIG. 21C to form the diamond composite IC wafer 1300 of FIG. 13 .

FIGS. 23A to 23C are schematic diagrams of manufacturing processes of the diamond composite IC wafer 1300 of FIG. 13 according to another embodiment of the present disclosure.

As shown in FIG. 23A, the first semiconductor wafer 1102 with the predetermined diameter D2 are prepared, wherein the first semiconductor wafer 1102 includes a set of IC circuits on a first side of the first semiconductor wafer 1102.

As shown in FIG. 23B, the diamond wafer 1301 with the predetermined diameter D2 and with spacers (not shown) is prepared.

As shown in FIG. 23C, the diamond wafer 1301 is bonded to the first semiconductor wafer 1102 to form the diamond composite IC wafer 1400′.

Then, at least one first semiconductor wafers 1102 is attached to the diamond wafer 1301 of the diamond composite IC wafer 1400′ of FIG. 23C to form the diamond composite IC wafer 1400 of FIG. 14 .

In another embodiment, at least one first semiconductor wafers 1102 and at least one diamond containing interposer 1203 of FIG. 15 may be bonded to the diamond composite IC wafer 1400′ of FIG. 23C to form the diamond composite IC wafer 1500 of FIG. 15 , wherein a plurality of the first semiconductor wafers 1102 and interposers are connected to each other by micro-bump or copper hybrid bonding.

FIGS. 24A to 24G are schematic diagrams of manufacturing processes of a diamond composite IC wafer according to another embodiment of the present disclosure.

As illustrated in FIG. 24A, a plurality of the composite block 800A of FIG. 8 are attached to the temporary carrier 10A with a release layer 20. Each composite block 800A includes the semiconductor block 531 and the diamond layer 810 formed on the semiconductor block 531 by, for example, CVD. In an embodiment, the semiconductor block 531 may be a silicon block cut form a silicon wafer. In another embodiment, the semiconductor block 531 may be a SiC block cut form a SiC wafer.

As illustrated in FIG. 24B, the gaps G1 between composite block 800A are filled with the spacer material 520′.

As shown in FIG. 24C, a portion of the spacer material 520′ is removed to form a plurality of the spacer 520 by using, for example, CMP, DRIE, etc. Each of the spacers 520 fills the gap G1 between two adjacent composite blocks 800A. Furthermore, the spacer material 520′ is planarized to expose the composite block 800A. After planarization, the spacers 520 each having the upper surface 520 u and the composite block 800A each having the upper surface 810 u are formed, and the upper surface 810 u and the upper surface 520 u flush with each other.

As shown in FIG. 24D, the temporary carrier 10A and the release layer 20 may be removed from the spacers 520 and the composite blocks 800A.

As shown in FIG. 24E, the structure in FIG. 24D is attached on a semiconductor substrate 230 by the release layer 20.

As shown in FIG. 24F, the semiconductor block 531 of the composite block 800A in FIG. 24E is removed by, for example, a CMP. As shown in FIG. 24G, the semiconductor substrate 230 and the release layer 20 may be removed from the spacers 520 and the diamond layers 810 to form a diamond composite wafer 100′.

In another embodiment, after the process in FIG. 24D, the semiconductor blocks 531 in FIG. 24D may be removed to form the diamond composite wafer 100′ as illustrated in FIG. 24G by, for example, a CMP.

FIGS. 25A to 25G are schematic diagrams of manufacturing processes of a diamond composite IC wafer according to another embodiment of the present disclosure.

As illustrated in FIG. 25A, a plurality of the composite blocks 900A of FIG. 19 are attached to the temporary carrier 10A. Each composite block 900A includes the diamond block 110 and the Si layer 8311 formed on the diamond block 110.

As illustrated in FIG. 25B, the gaps G1 between the composite blocks 900A are filled with the spacer material 520′.

As shown in FIG. 25C, a portion of the spacer material 520′ is removed to form a plurality of the spacer 520 by using, for example, CMP, DRIE, etc. Each of the spacers 520 fills the gap G1 between two adjacent composite blocks 900A. Furthermore, the spacer material 520′ is planarized to expose the composite block 900A. After planarization, the spacers 520 each having the upper surface 520 u and the composite block 900A each having the upper surface 110 u are formed, and the upper surface 110 u and the upper surface 520 u flush with each other.

As shown in FIG. 25D, the temporary carrier 10A and the release layer 20 may be removed from the spacers 520 and the composite blocks 900A.

As shown in FIG. 25E, the structure in FIG. 25D is attached on the semiconductor substrate 230 by the release layer 20.

As shown in FIG. 25F, the Si layer 8311 of the composite block 900A is removed by, for example, a CMP.

As shown in FIG. 25G, the semiconductor substrate 230 and the release layer 20 may be removed from the spacers 520 and the diamond blocks 110 to form a diamond composite wafer 100″.

In another embodiment, after the process in FIG. 25D, the Si layer 8311 of the composite block 900A is removed by, for example, a CMP to form the diamond composite wafer 100″ as illustrated in FIG. 25G.

As described above, a manufacturing method of a diamond composite wafer is provided. In an embodiment, diamond composite wafer includes at least one diamond block formed of diamond material. Accordingly, the diamond composite wafer has good theoretical semiconductor performance characteristics and good cooling performance.

In addition, the diamond composite wafer as aforementioned above could be integrated into a wafer IC.

FIG. 26 is a schematic diagram of a wafer IC 100A made of diamond composite wafers (or a diamond composite wafer) according to an embodiment of the present disclosure. The wafer IC 100A includes a diamond composite wafer 100A1, a first RDL 100A2, a second RDL 100A3, at least one through via 100A4, at least one first conductive pad 100A5 and at least one second conductive pad 100A6. The through vias 100A4 are formed within the diamond composite wafer 100A1. The first RDL 100A2 is formed on a first side S1 of the diamond composite wafer 100A1. The second RDL 100A3 is formed on a second side S2 of the diamond composite wafer 100A1.

As illustrated in FIG. 26 , the diamond composite wafer 100A1 includes the structure the same as or similar to those of the diamond composite wafer 100, 100′, 100″, 200, 400, 500, 700, 800, 900 or 1000. The diamond composite wafer 100A1 includes a diamond layer 100A11 and a semiconductor substrate 100A12. The diamond layer 100A11 includes the structure the same as or similar to those of the diamond block of the diamond composite wafer, and the semiconductor substrate 100A12 includes the structure the same as or similar to these of the semiconductor substrate of the diamond composite wafer.

Although not illustrated, a circuit structure (for example, wafer front-end-of-line (FEOL) layer and/or wafer back-end-of-line (BEOL) layer) could be formed on the semiconductor substrate 100A12 of the diamond composite wafer 100A1.

As illustrated in FIG. 26 , the through vias 100A4 are, for example, TSDVs. The through vias 100A4 could be formed of a conductive material, such as copper. The through vias 100A4 extend to the second side S2 of the diamond composite wafer 100A1 from the first side S1 of the diamond composite wafer 100A1, and electrically connect the first RDL 100A2 and the second RDL 100A3.

As illustrated in FIG. 26 , the first conductive pad 100A5 and the second conductive pad 100A6 are, for example, metal pad such as copper pad or metal pads with micro-bumps. The wafer IC 100A could be electrically connected to a circuit through the first conductive pad 100A5 and the second conductive pad 100A6.

FIG. 27 is a schematic diagram of a wafer IC 200A according to another embodiment of the present disclosure. The wafer IC 200A includes a diamond composite wafer 200A1, the first RDL 100A2, the second RDL 100A3, at least one through via 100A4, at least one first conductive pad 100A5 and at least one second conductive pad 100A6. The through vias 100A4 are formed within the diamond composite wafer 200A1. The first RDL 100A2 is formed on a first side S1 of the diamond composite wafer 200A1. The second RDL 100A3 is formed on a second side S2 of the diamond composite wafer 200A1.

As illustrated in FIG. 27 , the diamond composite wafer 200A1 includes the structure the same as or similar to those of the diamond composite wafer 100. The diamond composite wafer 200A1 is, for example, a diamond layer including the structure the same as or similar to these of the diamond block of the diamond composite wafer. Although not illustrated, a circuit structure (for example, wafer front-end-of-line (FEOL) layer and/or wafer back-end-of-line (BEOL) layer) could be formed on the diamond composite wafer 200A1.

Through vias in FIGS. 26 and 27 can provide the functions of electrical vias, optical vias, thermal vias and/or fluidic vias, whereas RDL can serve the purposes of not just electrical interconnection but also optical waveguide functions. Complex fluidic micro-channels for enhanced cooling can also be created by a combination of MEMS, wafer BEOL and advanced packaging technologies.

To create the diamond interposers in FIG. 27 from full-sized diamond wafers, one can begin with a diamond composite substrate (for instance, ˜100 μm thick, about the same thickness as a 2.5D silicon interposer) and subject it to deep reactive ion etching (DRIE; or the Bosch process) utilizing oxygen as the etch gas (and other heavier gases such as CF₄) and a mask such as aluminum/silicon dioxide, aluminum/silicon/aluminum, or stainless steel to create the high-aspect ratio through diamond vias, TDVs (e.g., thousands of them of 20 μm in diameter at an aspect ratio of 5) at high etch rates. Other mask choices that can be considered include aluminum, titanium, gold, chromium, silicon dioxide, aluminum oxide, photoresist and/or spin-on-glass. The etch mask material needs to be etched slower than diamond in DRIE with high selectivity. Ultra-short-pulse (e.g., femtosecond-pulsed) laser micromachining can also be used without the mask or in conjunction with DRIE to create TDV holes for improved etch performance. A combination of DRIE and epitaxial deposition can create ultra-high-aspect-ratio (up to 500) trenches in silicon. It may also be fashioned after to create ultra-high-aspect-ratio TDVs.

Following TDV hole opening, one can proceed to follow the standard 2.5D silicon interposer process flow starting from plasma enhanced chemical vapor deposition (PECVD) of oxide, and physical vapor deposition (PVD) of barrier/seed titanium/copper (Ti/Cu) or tantalum nitride/Cu (TaN/Cu) by sputtering to copper plating to fill the TDVs to chemical mechanical polish (CMP) to remove the overburden Cu and then to frontside (chip-side) μm-level fine-line RDL and under-bump metallurgy (UBM) processing. This is followed by post-TSV processes from carrier bond to wafer thinning to backside RDL and UBM to ball placement to die tape attach to carrier de-bond to dicing to singulate the interposer.

For full-sized silicon-diamond bi-wafers (and also tri-wafers), one can first follow the above diamond interposer process to create the TDVs in the silicon-diamond bi-wafer (or the silicon-diamond-silicon tri-wafer), followed by DRIE of silicon using fluorinated gases such as CF₄, SF₈ or xenon difluoride (i.e., the Bosch etch process) as the etch gas to create the through silicon vias (TSVs) on where the TDVs are with the assistance of alignment marks, forming the through diamond-silicon vias (TDSVs). Subsequently, one can resume the balance of the above diamond interposer process starting from the PECVD and PVD step to dicing. The process to create TDSV containing interposers can be used to create similar structures in active devices and interposers using bi-wafers or tri-wafers as the substrates.

With the use of 3D laser lithography, one can also form 3D micro-structures on the planar diamond or silicon-diamond bi-wafer interposer substrates or dies using greyscale photolithography which is a method to create 3D structures in the mask (e.g., photoresist, metal, oxide and their combinations), and transfer them through dry anisotropic etching to the substrate or die. In planar technologies used in for instance MEMS fabrication that involving the creation of MEMS microstructures in silicon (Si), usually only one exposure dose is applied. In greyscale photolithography, the exposure UV light intensity needs to be controlled and several methods such as multiple-step exposure, pixelated mask exposure and direct writing can be used to create the 3D structures.

FIGS. 28A to 28E are schematic diagrams of manufacturing processes of the wafer IC 100A of FIG. 26 according to an embodiment of the present disclosure.

As shown in FIG. 28A, a diamond composite wafer 100A1 is provided. The diamond composite wafer 100A1 includes the structure the same as or similar to those of the diamond composite wafer 200, 400, 500, 700, 800, 900 or 1000. The diamond composite wafer 100A1 includes the diamond layer 100A11 and the semiconductor substrate 100A12. The diamond layer 100A11 includes the structure the same as or similar to those of the diamond block of the diamond composite wafer, and the semiconductor substrate 100A12 includes the structure the same as or similar to those of the semiconductor substrate of the diamond composite wafer. In an embodiment, although not illustrated, a circuit structure (for example, wafer front-end-of-line (FEOL) layer and/or wafer back-end-of-line (BEOL) layer) could be formed on the semiconductor substrate 100A12 of the diamond composite wafer 100A1.

The diamond composite wafer 100A1 has the first side S1 and a second side S2′ opposite to the first side S1.

As shown in FIG. 28B, a plurality of the through vias 100A4 extending from the first side S1 of the diamond composite wafer 100A1 toward the second side S2′ of the diamond composite wafer 100A1. Then, the first RDL 100A2 is formed on the first side S1 of the diamond composite wafer 100A1. Then, at least one first conductive pad 100A5 are formed on the first RDL 100A2.

As shown in FIG. 28C, the structure of FIG. 28B is inverted and bonded to a temporary carrier with the use of a release layer (not shown) to expose the second side S2′.

As shown in FIG. 28D, a portion of the diamond layer 100A11 is removed to form the new second side S2 and a portion of the through via 100A4 is removed to form an terminal surface 100A41 by, for example, a CMP, wherein the second side S2 of the diamond layer 100A11 and the terminal surface 100A41 of the through via 100A4 flush with each other.

As shown in FIG. 28E, the second RDL 100A3 is formed on the second side S2 of the diamond composite wafer 100A1. Then, at least one second conductive pad 100A6 are formed on the second RDL 100A3.

Then, the temporary carrier 10D is released to expose the first RDL 100A2 and form the wafer IC 100A of FIG. 26 . In an embodiment, the wafer IC 100A could be singulated or diced to form at least one singulated wafer IC.

FIGS. 29A to 29E are schematic diagrams of manufacturing processes of the wafer IC 100A of FIG. 27 according to another embodiment of the present disclosure.

As shown in FIG. 29A, a diamond composite wafer 100A1′ is provided. The diamond composite wafer 100A1′ includes the structure the same as or similar to those of the diamond composite wafer 300 or 600. The diamond composite wafer 100A1′ includes the diamond layer 100A11, the semiconductor substrate 100A12 and the semiconductor substrate 100A13. The diamond layer 100A11 includes the structure the same as or similar to those of the diamond block of the diamond composite wafer, the semiconductor substrates 100A12 and 100A13 include the structure the same as or similar to those of the semiconductor substrate of the diamond composite wafer. In an embodiment, although not illustrated, a circuit structure (for example, FEOL/BEOL layers) could be formed on the semiconductor substrate 100A13 or 100A12 of the diamond composite wafer 100A1′.

The diamond composite wafer 100A1′ has the first side S1 and a second side S2′ opposite to the first side S1.

As shown in FIG. 29B, a plurality of the through vias 100A4 extending from the first side S1 of the diamond composite wafer 100A1 toward the second side S2′ of the diamond composite wafer 100A1. Then, the first RDL 100A2 is formed on the first side S1 of the diamond composite wafer 100A1. Then, at least one first conductive pad 100A5 are formed on the first RDL 100A2.

As shown in FIG. 29C, the structure of FIG. 29B is inverted and bonded to a new temporary carrier on the first RDL 100A2 exposing the surface S2′.

As shown in FIG. 29D, a portion of the diamond layer 100A11 is removed to form the second side S2 and a portion of the through via 100A4 is removed to form a terminal surface 100A41 by, for example, a CMP, wherein the second side S2 of the diamond layer 100A11 and the terminal surface 100A41 of the through via 100A4 flush with each other.

As shown in FIG. 29E, the second RDL 100A3 is formed on the second side S2 of the diamond composite wafer 100A1′. Then, at least one second conductive pad 100A6 are formed on the second RDL 100A3.

Then, the temporary carrier 10D is released to expose the first RDL 100A2 and form the wafer IC 100A of FIG. 26 . In an embodiment, the wafer IC 100A could be singulated or diced to form at least one singulated wafer IC.

FIGS. 30A to 30E are schematic diagrams of manufacturing processes of the wafer IC 200A of FIG. 27 according to an embodiment of the present disclosure.

As shown in FIG. 30A, the diamond composite wafer 200A1 is provided. The diamond composite wafer 200A1 includes the structure the same as or similar to those of the diamond composite wafer 100. The diamond composite wafer 200A1 has a first side S1 and a second side S2′ opposite to the first side S1. In an embodiment, although not illustrated, a circuit structure (for example, FEOL/BEOL) could be formed on the diamond composite wafer 200A1.

As shown in FIG. 30B, a plurality of the through vias 100A4 extending from the first side S1 of the diamond composite wafer 200A1 towards the second side S2′ of the diamond composite wafer 200A1. Then, the first RDL 100A2 is formed on the first side S1 of the diamond composite wafer 200A1. Then, at least one first conductive pad 100A5 is formed on the first RDL 100A2.

As shown in FIG. 30C, the structure of FIG. 30B is inverted and bonded to a new temporary carrier with the S2′ surface exposed.

As shown in FIG. 30D, a portion of the diamond composite wafer 200A1 is removed to form the second side S2 and a portion of the through via 100A4 is removed to form a terminal surface 100A41 by, for example, a CMP, wherein the second side S2 of the diamond composite wafer 200A1 and the terminal surface 100A41 of the through via 100A4 flush with each other.

As shown in FIG. 30E, the second RDL 100A3 is formed on the second side S2 of the diamond composite wafer 200A1. Then, at least one second conductive pad 100A6 are formed on the second RDL 100A3.

Then, the temporary carrier 10D is released to expose the first RDL 100A2 and form the wafer IC 200A of FIG. 27 . In an embodiment, the wafer IC 200A could be singulated or diced to form at least one singulated wafer IC.

FIG. 31 is a schematic diagram of a semiconductor structure 100B according to an embodiment of the present disclosure. The semiconductor structure 100B can be disposed on and electrically connected to a printed circuit board (PCB) 100B8 through a plurality of solder balls. The semiconductor structure 100B includes a substrate 100B1 and at least one circuit (a first circuit and/or a second circuit) containing composite block over the substrate 100B1 disposed on the PCB. The circuits may include at least one HBM (high-bandwidth-memory) DRAM (dynamic random-access memory) die 100B2, at least one base or control die 100B3, at least one processor 100B4, at least one memory 100B5, at least one logic die 100B6 and at least one silicon interposer 100B7. The substrate 100B is, for example, a laminate substrate.

As illustrated in FIG. 31 , in the present embodiment, the second circuit is disposed under the first circuit. The first circuit or the second circuit containing composite block further comprises a plurality of IC circuits. In addition, the first circuit or the second circuit containing composite block includes at least one through via and at least one RDL, wherein the through via is, for example, an electrical via, an optical via, a thermal via or a fluidic via, etc., and the RDL includes, for example, an electrical interconnection or an optical waveguide. The HBM DRAM die 100B2, the base die 100B3, the processor 100B4, the memory 100B5, the logic die 100B6 and the silicon interposer 100B7 can include the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The circuits can be electrically connected with each other through at least one through via, one RDL and/or at least one solder ball.

FIG. 32 is a schematic diagram of a semiconductor structure 100C according to another embodiment of the present disclosure. The semiconductor structure 100C can be disposed on and electrically connected to a printed circuit board 100B8 through a plurality of solder balls. The semiconductor structure 100C includes the substrate 100B1, at least one circuit (the first circuit and/or the second circuit) containing composite block over the substrate 100B1 and at least one hybrid bond 100C. The circuits may include at least one HBM DRAM die 100B2, at least one base die 100B3, at least one processor 100B4, at least one memory 100B5, at least one logic die 100B6 and at least one silicon interposer 100B7. In the present embodiment, two adjacent circuits can be connected to each other through at least one copper hybrid bond 100C. The HBM DRAM die 100B2, the base die 100B3, the processor 100B4, the memory 100B5, the logic die 100B6 and the silicon interposer 100B7 can include the features the same as or similar to those of the diamond composite wafers or IC wafers as described above.

FIG. 33 is a schematic diagram of a semiconductor structure 100D according to another embodiment of the present disclosure. The semiconductor structure 100D could be disposed on and electrically connected to a printed circuit board through a plurality of solder balls (not shown). The semiconductor structure 100D includes the substrate 100D1 and at least one circuit 100D2 (the first circuit and/or the second circuit), an encapsulant 100D3 and a RDL 100D4. The encapsulant 100D3 encloses the circuits, and the RDL 100D4 is formed on the circuits and the encapsulant 100D3 and is electrically connected to the circuits. The substrate 100D1 is, for example, a laminate substrate. The circuit 100D2 is, for example, an IC. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above.

FIG. 34 is a schematic diagram of a semiconductor structure 100E according to another embodiment of the present disclosure. The semiconductor structure 100E can be disposed on and electrically connected to a printed circuit board through a plurality of solder balls (not shown). The semiconductor structure 100E includes the substrate 100E1 and at least one circuit 100D2 (the first circuit and/or the second circuit), an encapsulant 100D3, a RDL 100D4 and at least one copper hybrid bond 100C. In the present embodiment, the RDL 100D4 and the substrate 100E1 can be connected to each other through at least one hybrid bond 100C. The substrate 100E1 is, for example, an interposer. The circuit 100D2 includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above.

FIG. 35 is a schematic diagram of a semiconductor structure 100F according to another embodiment of the present disclosure. The semiconductor structure 100F can be disposed on and electrically connected to a printed circuit board 100B7 through a plurality of solder balls. The semiconductor structure 100F includes the substrate 100B and at least one circuit (the first circuit and/or the second circuit) containing composite block over the substrate 100B1. The circuits may include at least one HBM DRAM die 100B2, at least one base die 100B3, at least one processor 100B4, and at least one logic die 100B6. The component 100F5 is disposed on and electrically connected to the logic die 100B6. The base die 100B3 and the logic die 100B6 are disposed on and electrically connected to the substrate 100B1 side-by-side. The substrate 100B1 is embedded with an electronic component 100F1 which can be an active IC or a passive device. The electronic component 100F5 is, for example, a CPU, a GPU, a FPGA, a memory die, a memory die stack or a RF die. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. In FIG. 35 , flip chip assembly based on copper pillar micro-bumps or solder bumps is employed to electrically connect two electronic components, for instance, 100F5 and 100B6.

FIG. 36 is a schematic diagram of a semiconductor structure 100G according to another embodiment of the present disclosure. The semiconductor structure 100G could be disposed on and electrically connected to a printed circuit board 100B7 through a plurality of solder balls. The semiconductor structure 100G includes the substrate 100B1, at least one circuit (the first circuit and/or the second circuit) containing composite block over the substrate 100B1 and at least one copper hybrid bond 100C1. In the present embodiment, two adjacent circuits can be connected to each other through at least one hybrid bond 100C1. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The semiconductor structure 100G is substantially similar to the semiconductor structure 100F (in FIG. 35 ) with copper hybrid bonding assumed in forming the semiconductor structure 100G as opposed to flip chip assembly used in forming the semiconductor structure 100F.

FIG. 37 is a schematic diagram of a semiconductor structure 100H according to another embodiment of the present disclosure. The semiconductor structure 100H can be disposed on and electrically connected to a printed circuit board through a plurality of solder balls (not shown). The semiconductor structure 100H includes a substrate 100H1 and at least one circuit (the first circuit and/or the second circuit) containing composite block over the substrate 100H1. The circuits may include at least one processor 100H2 and a module 100H3, wherein the processor 100H2 is, for example, ASIC, a FPGA, CPU, etc., and the module 100H3 includes a silicon interposer 100H31 with wave guides and an optical module 100H32 disposed on the silicon interposer 100H31. The module 100H3 and the processor 100H2 are disposed on the substrate 100H1 side-by-side. The substrate 100H1 is, for example, a laminate substrate or a silicon interposer. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. In FIG. 37 , flip chip assembly based on copper pillar micro-bumps or solder bumps is employed to electrically connect two electronic components, for instance, 100H32 and 100H31.

FIG. 38 is a schematic diagram of a semiconductor structure 100I according to another embodiment of the present disclosure. The semiconductor structure 100I can be disposed on and electrically connected to a printed circuit board through a plurality of solder balls (not shown). The semiconductor structure 100I includes a substrate 100I1 and at least one circuit (the first circuit and/or the second circuit) containing composite block over the substrate 100I1. The circuits may include at least one processor 100H2 and a module 100H3. The substrate 100I1 is, for example, a laminate substrate or a silicon interposer. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The semiconductor structure 100I is substantially similar to the semiconductor structure 100H (in FIG. 37 ) with copper hybrid bonding assumed in forming the semiconductor structure 100I as opposed to flip chip assembly used in forming the semiconductor structure 100H.

In FIGS. 31 to 38 , a new breed of advanced ICs and advanced SiPs can be created using diamond (or other high-TC materials)composite wafers or IC wafers to form the electronic components in advanced SiPs comprising 2.5D IC, 3D IC, fan-out, embedded SiP and processor-(silicon) photonics SiP co-package. as shown in FIGS. 31 to 38 . Either solder bonding and/or copper hybrid bonding can be applied to join and electrically connect two electronic components in these structures as well as in other structures created by combining the technologies shown in FIGS. 31 to 38 . When a laminate substrate is involved, the dielectric for direct bonding preferably is a polyimide on both the interposer and the laminate substrate at the bonding interface. In other cases, the dielectric can be an oxide such as silicon dioxide (SiO₂).

For advanced SiPs, whether they be based on copper hybrid bonds or micro-bumps for interconnection, the packages can be subjected to air cooling and liquid cooling covering direct-to-chip liquid cooling and liquid immersion cooling. Immersion cooling involves the use of a dielectric coolant which is not electrically conductive, or both water and a conformal coating such as Parylene as water is electrically conductive. For copper hybrid bonding, one can choose oxide-to-oxide bonding or polyimide (PI)-to-PI bonding for bonding two IC wafers or two electronic components using silicon dioxide (SiO₂) or PI as the BEOL dielectric/bonding layers.

Direct oxide-to-oxide bonding proceeds generally in the following process sequence: (1) formation of dangling bonds and bonding between hydroxyl groups and water molecules through plasma activation using gases such as O₂ (oxygen)/N₂ (nitrogen)/Ar (argon): (2) removal of defects through deionized water cleaning and scrubbing; (3) bonding of wafers (or wafer and wafer-sized interposer) with oxide bonding layers at room temperature and atmospheric pressure via van der Waals hydrogen bonds between two to three monolayers of water molecules and polar hydroxyl (OH) groups (which terminate at both the native and thermal SiO₂); (4) formation of van der Waals bonds between H₂O molecules and silanol groups (Si—OH—(H₂O)x-HO—Si; silanol group ═Si—OH) on the top and bottom wafer surfaces; and (5) annealing to remove water molecules at the interface and form covalent bonds at temperatures typically less than 400° C. Void formation caused by water droplet formation (the Joule-Thomason expansion effect) at wafer edge during direct bonding must be avoided by controlling key parameters such as plasma conditions, surface roughness, degree of cleanliness, wafer warpage/flatness and bonding conditions. In the case of oxide-to-oxide bonding, one can also vary oxide type and deposition technique, process conditions such as plasma gas, plasma power, surface roughness pertaining to chemical mechanical polish (CMP), surface cleanliness, mono- to multiple layers of water molecules from de-ionized cleaning, bonding conditions (such as temperature and speed), and anneal conditions (e.g., anneal temperatures, anneal time and number of annealing steps) to maximize the bonding yield and shear strength between two wafers.

Regarding PI-to-PI bonding using fully cured polyimide-to-fully cured polyimide bonding based on pyromellitic dianhydride (PMDA) and 4,4′-diaminodiphenyl ether (4,4′-ODA) as an example, one can maximize the shear strength by varying conditions such as volume of water introduced, bonding time, and oxygen (O₂) plasma activation time. To achieve void-free PI-to-PI bonding, it is important to activate the PI surfaces by oxygen plasma activation to generate low-density hydrophilic groups on the PI surface which effectively enhances adsorption of water molecules introduced by a de-ionized water wetting process. The adsorbed water molecules, in turn, brings in considerable high-density OH (hydroxyl) groups which facilitate pre-bonding. Following PI surface activation and wetting, PI-to-PI hybrid bonding can take place at a relative low temperature of, for instance, 250° C. for a few minutes under, preferably, an external pressure. Neither the plasma process nor the wetting or hydration process alone can achieve good bonding. Key parameters to manipulate in order to achieve good bond yield include applied pressure during bonding, plasma activation time, volume of water introduced, bonding temperature and bonding time.

Oxide-to-oxide hybrid bonding requires high component flatness and surface cleanliness to avoid electrical interconnection fails due to silicon dioxide's high hardness and poor deformation characteristics. Compared to the conventional oxide-to-oxide hybrid bonding, PI-to-PI bonding allows for higher surface roughness and is more tolerant of component flatness due to the low modulus and more compliant characteristics of the Pls.

The explosion in data is driving extraordinary growth in internet traffic and cloud services. Silicon photonics will take the center stage in defining new mega data center architectures in order to manage the unabated growth in data traffic. New microelectronics packaging technologies are required to address optical-to-electrical interconnection as photon and electron exchanges move from optical transceivers mounted at the edge of server boards (in server racks inside mega data centers) to IC packages and logic chips inside these computing systems. Optics has traditionally been deployed to transmit data over long distances because light can carry considerably more information content (bits) at faster speed and light is more energy efficient compared to electronic alternatives to transmit data when the transmission length and bandwidth increases. Optical transceivers represent the initial high volume application for silicon photonics starting from 100 G as optics migrates as close as possible to the source of the data, resulting in large distances between the optical components and the processor chip. Using the silicon interposer based optical module (the top structure in FIGS. 37 and 38 ) as an example, its performance can be greatly enhanced by replacing the silicon interposer with a silicon-diamond bi-wafer interposer containing backside power supply and both optical waveguides and active and passive functions in silicon. Using a combination of photolithography, reactive ion etching (RIE) and focused ion beam techniques, one can also fabricate in the silicon portion of the bi-wafer optical chip that integrates function elements such as X-crossings, Y-functions, evanescent couplers, Bragg reflectors/couplers and various interferometers. As the need for higher data transfer speeds at greater baud rates and lower power levels intensifies, the trend is for optics to be moved even closer to the die. To this end, optoelectronic interconnect will need to be designed to interface directly to the processor, whether it be application specific integrated circuit (ASIC) or FPGA, to support switching, transceiver, signal conditioning and multiplexer/demultiplexer applications. This requires co-packaging of the optical module based on a silicon interposer with processor such as silicon based ASIC/FPGA/CPU (or its chiplets) flip chip bonded to a laminate substrate (see the top structure of FIGS. 37 and 38 ). As in the case of silicon-diamond bi-wafer enhanced optical module, the performance of this more complex SiP can be greatly enhanced by mounting the bi-wafer enabled optical module and the bi-wafer enabled ASIC/FPGA/CPU (with a diamond heat spreader attached) on a diamond or silicon-diamond interposer as shown in FIGS. 37 and 38 .

FIGS. 39 to 42 show four direct-to-chip liquid cooling structures. FIG. 39 is a schematic diagram of a semiconductor structure 100J according to another embodiment of the present disclosure. The semiconductor structure 100J includes a substrate 100J1, a cold plate 100J2, a plurality of circuits (the first circuit and/or the second circuit) 100J3, a plurality of high-thermal-conductivity (TC), low-coefficient-of-thermal-expansion (CTE) heat spreaders 100J4 (e.g., diamond heat spreaders and interposers) and a high-TC thermal interface material or a diamond layer 100J5. The substrate 100J1 is, for example, a laminate substrate. The cold plate 100J2 is disposed on the topmost circuit 100J3 or the topmost heat spreaders 100J4 for dissipating the heat generated by the circuits 100J3. The circuits 100J3 and the heat spreaders and interposers 100J4 are stacked to each other, wherein one heat spreader and interposer 100J4 may be formed between two adjacent circuits 100J3. The circuit includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. A high-TC thermal interface material or a diamond layer 100J5 can be disposed between the cold plate 100J2 and the topmost circuit 100J3.

FIG. 40 is a schematic diagram of a semiconductor structure 100K according to another embodiment of the present disclosure. The semiconductor structure 100K includes a substrate 100K1, a cold plate 100K2, a plurality of circuits (the first circuit and/or the second circuit) 100K3 and an interposer 100K4. The substrate 100K1 is, for example, a laminate substrate. The circuits 100K3 are stacked to each other. The circuit 100K3 and the interposer 100K4 include the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The cold plate 100K2 is disposed on the topmost circuit 100K3 for dissipating the heat generated by the circuits. The interposer 100K4 is disposed between the substrate 100K1 and the bottom circuit 100K3, and the interposer 100K4 can dissipate the heat generated by the circuits 100K3. The interposer 100K4 with circulating liquid coolant includes at least one fluidic via for conducting the heat generated by the circuits 100K3.

FIG. 41 is a schematic diagram of a semiconductor structure 100L according to another embodiment of the present disclosure. The semiconductor structure 100L includes a substrate 100L1 and a plurality of circuits (the first circuit and/or the second circuit) 100L3. The substrate 100L1 is, for example, a laminate substrate. The circuits 100L3 are stacked to each other. The circuit 100L3 includes the features the same as or similar to those of the diamond composite wafers or IC wafers. The circuit 100L3 further includes at least one fluidic via and/or at least one channel for conducting the heat generated by the circuits 100L3.

FIG. 42 is a schematic diagram of a semiconductor structure 100M according to another embodiment of the present disclosure. The semiconductor structure 100M includes a substrate 100M1 and a plurality of circuits (the first circuit and/or the second circuit) 100M3. The substrate 100M1 is, for example, a laminate substrate. The circuits 100M3 are stacked to each other. The circuit 100M3 includes the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The circuit 100M3 further include at least one fluidic via and/or at least one fluidic channel for conducting the heat generated by the circuits 100M3.

FIG. 43 is a schematic diagram of a semiconductor structure 100N according to another embodiment of the present disclosure. The semiconductor structure 100N includes a substrate 100N1 containing fluidic micro-channels, a cold plate 100N2, a plurality of circuits 100N3, a plurality of high-TC interposers (e.g., diamond interposers) with through vias (see the shaded areas in FIG. 43 ) 100N4, a diamond layer 100N5 which can also be a high-TC thermal interface material (TIM), or a diamond (or vapor chamber)—TIM composite structure, a structural member or port 100N6 which is fluidly coupled to the cold plate 100N2 and the substrate 100N1, and a manifold 100N7 which is fluidly coupled to the cold plate 100N2. The diamond layer can be larger in size compared to the top circuit 100N3 for more efficient heat dissipation. The circuits 100N3 are packaged with the interposers (e.g., diamond interposers) containing electrical though vias and redistribution/bonding layers on both the top and bottom sides 100N4 in between two adjacent circuits 100N3 and the resultant 3D IC structure is disposed on the substrate 100N1. The substrate 100N1 is, for example, a silicon interposer with electrical, optical and fluidic vias. The circuit 100N3 and the interposer 100N4 include the features the same as or similar to those of the diamond composite wafers or IC wafers as described above. The structural member or port 100N6 surrounds the circuits 100N3, wherein the structural member 100N6 includes at least one fluidic channel 100N61 fluidly coupled to the fluidic via of the substrate 100N1. Through vias in the circuits 100N3, the interposers 100N4 and the substrate 100N1 can be electrical vias, thermal vias, optical vias, fluidic vias or combinations thereof. Redistribution layers pertaining to the circuits 100N3, the interposers 100N4 and the substrate 100N1 can contain electrical wiring and/or optical waveguides.

The incorporation of the interposer substrate 100N1 containing fluidic micro-channels allows for heat dissipation to take place from both the front-side and the backside of the chips. The interposer can be of a dual-shell construction with two interposer shells separately constructed and bonded together to increase (e.g., double) the heights and spaces of the cavity and fluidic micro-channels created between through via arrays 100N10 for enhanced cooling efficiencies. The interposer can be made of silicon or other suitable materials that are amenable to microfabrication. Bonding of the two interposer shells can be achieved through a multiplicity of seal rings 100N11 shown in FIG. 43 (bottom right) with each seal ring consisting of a bottom portion and a matching top portion (not shown) mimicking, for instance, flip chip bonding structures (e.g., solder on the top seal ring and matching bottom seal ring with proper surface metallurgy to facilitate wetting of molten solder and a solder dam) with the use of a non-conductive paste/film as warranted as in micro-bump based flip chip assembly. All through vias 100N12 are embedded in and are protected by the interposer substrate material 100N13, e.g., silicon. The multiple seal ring structure can also be replaced by a single large seal ring extending from the innermost seal ring 100N11 (FIG. 43 ) all the way to the edge of the through via cylinder to achieve hermetic sealing against the liquid coolant. In FIG. 43 , the coolant (e.g., water) is injected and drained through the port 100N6 which is connected to the cold plate 100N2.

In addition to using water as the coolant, a dielectric liquid coolant can be used to cool the semiconductor structure 100N and the circuits 100N3. The circuits 100N3 and the diamond interposers 100N4, and the bottom circuit 100N3 and the substrate 100N1 can be bonded through copper hybrid bonding based on oxide-to-oxide bonding or polyimide (PI)-to-PI bonding, or flip chip bonding.

The diamond layer 100N5 can be deposited on the side to be bonded to the backside of the circuit 100N3 with a surface layer 100N51 that forms chemical bonds with diamond such as Ti and at least one bonding layer 100N8 such as Au (or other materials such as a solder or a transient liquid phase material), and a side (i.e., the backside) of the circuit 100N3 (for example, silicon) is deposited with a good diffusion barrier layer 100N9 such as Ti, TiN, Ti/TIN or Ti/Ni and a bonding layer 100N8 such as Au or a solder to enable low-temperature diamond layer 100N5 to IC circuit 100N3 bonding at temperatures preferably below 300° C. The diamond layer 100N5 can be bonded on the side opposite to the circuit 100N3 side to the cold plate 100N2 using a TIM 100N81.

Although the IC circuits 100N3 and the high-TC interposers 100N4 are of the same sizes as shown in FIG. 43 for illustration, they can be of different sizes. High-end processors are typically larger than memory dies. Though not shown in FIG. 43 , the high-TC interposers 100N4 which are inserted between IC circuits 100N3 can also be placed between the IC circuits and/or side-by-side with the IC circuits 100N3 at each circuit layer as needed to form the 3D structures to enhance localized heat dissipation. These statements apply to other figures in this invention and will not be repeated for brevity.

FIG. 44 is a schematic diagram of a semiconductor structure 100P according to another embodiment of the present disclosure. The semiconductor structure 100P includes a substrate 100P1 containing fluidic micro-channels, a cold plate 100P2, a plurality of circuits (the first circuit and/or the second circuit) 100P3, a diamond layer 100P5 which can also be a high-TC thermal interface material (TIM), or a diamond (or vapor chamber)—TIM composite structure, a structural member or port 100P6 which is fluidly coupled to the cold plate 100P2 and the substrate 100P1, and a manifold 100P7 which is fluidly coupled to the cold plate 100P2. The diamond layer can be larger in size compared to the top circuit 100P3 for more efficient heat dissipation. The circuits 100P3 differ from the circuits 100N3 in FIG. 43 in that the former circuits 100P3 are made of the diamond composite wafers or IC wafers as described above (with the diamond portion of the circuit 100P3 either facing up or down as needed) while the latter circuit 100N3 are made of semiconductor materials such as silicon or silicon carbide. In FIG. 44 , no interposers between circuits 100P3 are needed. The circuits 100P3 with the exception of the top circuit 100P3 can contain electrically conductive through vias and redistribution/bonding layers on both the top and bottom sides. Thermal through vias (e.g., copper vias) as shown in FIG. 44 can also be created in the top circuit 100P3 to facilitate heat dissipation from the circuits 100P3 towards the cold plate 100P2. Through vias in the circuits 100P3, and the substrate 100P1 can be electrical vias, thermal vias, optical vias, fluidic vias or combinations thereof. Redistribution layers pertaining to the circuits 100P3, and the substrate 100P1 can contain electrical wiring, and/or optical waveguides.

The substrate 100P1 is, for example, a silicon interposer containing fluidic micro-channels. The circuits 100P3 are stacked to each other and together disposed on the substrate 100P1. The structural member or port 100P6 surrounds the circuits 100P3, wherein the structural member or port 100P6 includes at least one fluidic channel 100N61 fluidly coupled to the fluidic via of the substrate 100P1.

The incorporation of the interposer substrate 100P1 containing fluidic micro-channels allows for heat dissipation to take place from both the front-side and the backside of the chips. The interposer can be of a dual-shell construction with two interposer shells separately constructed and bonded together to increase (e.g., double) the heights and spaces of the cavity and fluidic micro-channels created between through via arrays 100P10 for enhanced cooling efficiencies. The interposer can be made of silicon or other suitable materials that are amenable to microfabrication. Bonding of the two interposer shells can be achieved through a multiplicity of seal rings 100P11 shown in FIG. 44 (bottom right) with each seal ring consisting of a bottom portion and a matching top portion (not shown) mimicking flip chip bonding structures (e.g., solder on the top seal ring and matching bottom seal ring with proper surface metallurgy to facilitate wetting of molten solder and a solder dam) with the use of a non-conductive paste/film as warranted as in micro-bump based flip chip assembly. All through vias 100P12 are embedded in and are protected by the interposer substrate material 100P13, e.g., silicon. The multiple seal ring structure can also be replaced by a single large seal ring extending from the innermost seal ring 100P11 (FIG. 44 ) all the way to the edge of the through via cylinder to achieve hermetic sealing against the liquid coolant. In FIG. 44 , the coolant (e.g., water) is injected and drained through the port 100P6 which is connected to the cold plate 100P2.

In addition to using water as the coolant, a dielectric liquid coolant can be used to cool the semiconductor structure 100P and the circuits 100P3. The circuits 100P3 can be bonded to each other and the bottom circuit 100P3 can be bonded to the interposer substrate 100P1 through copper hybrid bonding based on oxide-to-oxide bonding or polyimide (PI)-to-PI bonding, or flip chip bonding.

The diamond layer 100P5 can be deposited on the side to be bonded to the circuit 100P3 with a surface layer 100P51 that forms chemical bonds with diamond such as Ti and at least one bonding layer 100P8 such as Au (or other materials such as a solder or a transient liquid phase material), and the diamond side of the circuit 100P3 can be deposited with a suitable metallurgy (e.g., Ti/Au) to enable low-temperature bonding of the diamond layer 100P5 to the backside of the circuit 100P3 at preferably below 300° C. The diamond layer 100P5 can be bonded on the side opposite to the circuit 100P3 side to the cold plate 100P2 using a TIM 100P81.

The methodologies, 3D structures and processes illustrated in FIGS. 43 and 44 can be applied to and/or combined with the structures shown in FIGS. 31 to 42 and their combinations when direct-to-chip liquid cooling is used.

The direct-to-chip liquid cooled 3D structures shown in FIGS. 43 and 44 are for high-end HPC, data center and AI applications involving high processor powers. For PC and smart handheld applications which rely on air cooling (with a fan space permitting) and involve smaller processor powers, different air cooled 3D structures are needed. FIG. 45 is a schematic diagram of an air cooled semiconductor structure 100Q according to another embodiment of the present disclosure. The semiconductor structure 100Q includes a high-TC substrate 100Q1, a high-TC heat spreader or lid 100Q2 (e.g., copper lid or vapor chamber), a plurality of circuits 100Q3, a diamond layer 100Q5 which is bonded to the backside of the circuit 100Q3 as described in FIGS. 43 and 44 (with a TIM in between the diamond layer 100Q5 and the heat spreader 100Q2) and which can also be a high-TC TIM or a diamond (or vapor chamber)-TIM composite structure, a high-TC structural member 100Q6 and a high-TC heatsink 100Q7 thermally coupled to the heat spreader 100Q2. The diamond layer can be larger in size compared to the top circuit 100Q3 for more efficient heat dissipation. The high-TC substrate 100Q1 is, for example, a silicon-diamond interposer. The circuits 100Q3 can be made of diamond composite wafers or IC wafers (e.g., the bottom two circuits; FIG. 45 ) with the diamond portion of the circuit either facing up or down as needed, and/or of silicon or silicon carbide (e.g., the topmost circuit; FIG. 45 ). As illustrated in FIG. 45 , the bottom two chips and the substrate 100Q1 can contain through vias and redistribution/bonding layers on both the top and bottom sides of each circuit 100Q3 and the substrate, whereas the top circuit 100Q3 can contain thermal vias (see FIG. 45 ). The circuits 100Q3 are stacked to each other and together disposed on the substrate 100Q1. The circuits 100Q3 can be bonded to each other and the bottom circuit 100Q3 can be bonded to the interposer substrate 100Q1 through copper hybrid bonding based on oxide-to-oxide bonding or polyimide (PI)-to-PI bonding, or flip chip bonding. The high-TC structural member 100Q6 surrounds the circuits 100Q3, and is thermally coupled to the high-TC substrate lid and the heat spreader 100Q2. Through vias in the circuits 100Q3, and the substrate 100Q1 can be electrical vias, thermal vias, optical vias, fluidic vias or combinations thereof. Redistribution layers pertaining to the circuits 100Q3, and the substrate 100Q1 can contain electrical wiring, and/or optical waveguides.

FIG. 46 is a schematic diagram of another air cooled semiconductor structure 100R according to another embodiment of the present disclosure. The semiconductor structure 100R includes a high-TC substrate 100R1, a plurality of circuits 100R3 and a diamond layer 100R5 which is bonded to the backside of the top circuit 100R3 as described in FIG. 46 , and which can also be a vapor chamber bonded to the backside of the top circuit 100R3 with a TIM. The diamond layer 100R5 can be larger in size compared to the top circuit 100R3 for more efficient heat dissipation. The substrate 100R1 is, for example, a silicon-diamond interposer containing through vias and redistribution/bonding layers on its top side and its bottom side. The substrate 100R1 and the circuits 100R3 can be made of diamond composite wafers or IC wafers as in the case of the semiconductor structure 100Q (FIG. 45 ), and/or of silicon or silicon carbide. As illustrated in FIG. 46 , the bottom two chips and the substrate 100R1 can contain through vias and redistribution/bonding layers on both the top and bottom sides of each circuit 100R3 and the substrate, whereas the top circuit 100R3 can contain thermal vias (see FIG. 46 ). The circuits 100R3 are stacked to each other and together disposed on the substrate 100R1. The circuits 100R3 can be bonded to each other, and the bottom circuit 100R3 and substrate 100R1 can be bonded through copper hybrid bonding based on oxide-to-oxide bonding or polyimide (PI)-to-PI bonding, or flip chip bonding. Through vias in the circuits 100R3, and the substrate 100R1 can be electrical vias, thermal vias, optical vias, fluidic vias or combinations thereof. Redistribution layers pertaining to the circuits 100R3, and the substrate 100R1 can contain electrical wiring, and/or optical waveguides.

The methodologies, 3D structures and processes illustrated in FIGS. 45 and 46 can also be applied to and combined with the structures shown in FIGS. 31 to 42 and their combinations when air cooling is used.

The embodiment of combinations of the structures of FIGS. 39 and 40 are demonstrated in FIGS. 43 and 44 which show 3D IC stacks built, respectively, by (a) active silicon ICs with diamond interposers in between ICs (see FIG. 43 ), and (b) bi-wafer and/or tri-wafer enabled ICs without diamond interposers (see FIG. 44 ) while both 3D IC stacks are interconnected to an interposer containing fluidic micro-channels. In either case, the 3D IC on interposer which is cooled from the top and bottom sides is encased in an enclosure defined by a cold plate that can be bonded to the backside of the chip on top of the three-die stack using diamond as shown in FIG. 43 , structural members surrounding the 3D IC and the interposer with fluidic channels as shown in FIGS. 43 and 44 . The cold plate can be a vapor chamber or a cold plate containing fluidic micro-channels. The cold plates and structural members can be made of copper, silicon or other materials such as diamond. In the cases of silicon and diamond, these structural members and cold plate can be machined and created using MEMS, wafer BEOL and advanced packaging processes and materials. The interconnections in FIGS. 43 and 44 between ICs, and between IC and interposer can be achieved by oxide-to-oxide based copper hybrid bonding. FIG. 45 shows a counterpart of FIG. 44 for applications that do not use liquid cooling through micro-channels. In this case, the 3D IC is cooled by a combination of a lid or heat spreader, and a heatsink. The lid can be a vapor chamber, cooled by a capillary vapor phase cooling mechanism. The structure shown in FIG. 45 without the heatsink can be readily extended to immersion cooling by dunking the structure with the lid in cooling liquid. FIG. 46 , on the other hand, shows for air cooled smart handhelds where space is a premium, 3D IC cooling with the assistance of diamond composite wafer based ICs and interposers for enhanced thermal management but with the use of a heat spreader/heatsink (not shown) such as a vapor chamber which can be integrated with, for instance, the back covers of handheld devices. Cooling of the structures shown in FIGS. 43 and 44 can be farther enhanced by incorporating micro-jet through tiny channels formed on top of the top chip. and/or by other liquid cooling technologies such as inclusion of fluidic micro-channels in active ICs and even liquid immersion cooling to achieve cooling of chips beyond 1000 W. The methodologies, 3D structures and processes illustrated in FIGS. 43 and 44 can also be applied to and/or combined with the structures shown in FIGS. 31 to 42 and their combinations when liquid immersion cooling is used with, for instance, the fluidic vias in the interposer substrate serving as the open access holes for the liquid immersion coolant to use and cool the bottom chip/circuit on the interposer. Coolants used for liquid immersion cooling comprise dielectric coolants and water.

Today, air cooling is still the norm at data centers and many enhanced cooling methodologies (e.g., calibrated vectored cooling, cold aisle/hot aisle containment, computer room air conditioner, etc.) are being implemented to enhance the efficiencies of air cooling. These improvements tend to be offset, however, by the ever-increasing processor power and amounts of compute and storage required to satisfy the insatiable demands of consumers for more data. Although air cooling technology has improved significantly in the recent past, it suffers from significant energy costs, a large data center space required, introduction of moisture into sealed environments, and frequent mechanical failures (e.g., related to fans). To cope with the escalating data traffic, data centers are starting to experiment on liquid cooling technologies such as direct-to-chip liquid cooling which have been demonstrated to provide increased efficiency and effectively in cooling. Compared to air cooling systems which require a lot of power and bring with them pollutants and condensation into the data centers, liquid cooling systems can require less energy and lower operating cost, be cleaner, be more scalable, and be less dependent on climate and location.

There exist two common liquid cooling systems: liquid immersion cooling and direct-to-chip cooling. Immersion cooling involves physically submerging computer components (e.g., the server board mounted with SiPs and IC packages) in a tub of a dielectric coolant which can be a fluorocarbon or a hydrocarbon that possesses higher thermal conductivity than air. The dielectric coolant is thermally but not electrically conductive and is therefore safe for computer components during liquid immersion cooling. Both the fluid coolant and the hardware are contained within a leak-proof container. Liquid immersion cooling uses liquid to directly come in contact with the heat source (i.e., the hot chips) for better heat dissipation. The dielectric coolant absorbs heat far more efficiently than air, and as heated water (at the CDU, see below) turns to vapor, the coolant condenses and falls back into the fluid to aid in cooling. Direct-to-chip cooling utilizes pipes that deliver liquid coolant directly into a cold plate that sits atop, for instance, a server board's chips to draw off heat. The extracted heat is subsequently fed to chilled-water loop to be transported back to the facility's cooling plant and released into the outside atmosphere. Direct-to-chip cooling may use either dielectric or non-dielectric fluids (e.g., water). Although both methods provide far more efficient cooling solutions than air cooling for power-hungry data center deployments, liquid immersion cooling involving directly immersing chips in liquid can be far more effective in carrying the heat away from chip hot spots compared to direct-to-chip cooling where the fluid never makes direct contact with the hot chips.

Liquid immersion cooling can be carried out via single-phase cooling or two-phase cooling. State-of-the-art immersion cooling systems today still rely on the use of non-electrically-conductive dielectric coolants for heat transfer. Single-phase and two-phase cooling systems do not require cooling fins and fans in the IT equipment, machine room refrigerated air conditioning system, raised access floor, etc. required by air cooling.

In a single-phase liquid immersion cooling system, the server boards are typically immersed in a tank in a dielectric coolant and heat generated by server boards is conducted through the direct contact between the coolant and the components on server boards. Unlike two-phase liquid immersion cooling, single-phase cooling system requires a pump in the coolant distribution unit (CDU) to suck the fluid into the CDU that is equipped with a coolant-to-water heat exchanger for cooling, which, in turn, is cooled using an additional heat rejection equipment to complete the heat exchange cycle. Due to the high boiling point of the liquid coolant used, the liquid will not vaporize so the liquid tank of a single-phase liquid immersion cooling system does not require a strict sealed design and environmental controls.

In a two-phase liquid immersion cooling system, server boards are immersed in a specially designed “sealed” tank that uses typically a low-boiling-point dielectric coolant so that the heat generated by server boards can easily cause a phase change where the fluid surrounding the components boils and generates vapor, which, in turn, undergoes phase change through the condenser, returning the coolant to the liquid state while removing the heat. The sealed tank maintains the phase change process through environmental controls, and the heat exchange process continues.

Although both single-phase cooling and two-phase cooling can be deployed with this invention based on the use of an appropriate dielectric coolant, electrically conductive water and water-based fluids present advantages over dielectric coolants, and the conformal parylene coating disclosed herein allows them to be used as an option. As reported by the paper (Birbarah, et al., “Water Immersion Cooling of High Power Density Electronics,” International Journal of Heat Transfer, 147 (2020) 118918):

-   -   Single-phase cooling is limited to relatively low heat transfer         coefficients (<2 kW/m²/K). On other hand, two-phase cooling may         suffer from hydrodynamic instabilities. The ultra-high latent         heat of phase change (2.4 MJ/kg for water-glycol mixture vs. 0.3         MJ/kg for dielectric fluids) and surface tension (50 to 73 mN/m         for water-glycol mixtures vs. 5 mN/m for dielectric fluids) of         water and water-glycol mixtures enable highly efferent pool         boiling heat transfer that can come with an order of magnitude         higher critical heat flux when compared to dielectric coolants,         and     -   Furthermore, operating temperatures of electronics at         atmospheric pressures could be extended to 100° C. for water or         higher for water glycol mixtures (107° C. for water-ethylene         glycol mixture of 50%-50% by volume).

Water-based fluids are currently utilized in many applications including automotive cooling and would therefore eliminate the need for additional working fluids for immersion cooling of electronics in these applications. To enable the use of water-based coolants, the 2.5D IC and 3D IC structures for liquid immersion cooling, however, must be sealed and protected with a pin-hole-free conformal coating such as parylene due to the electrical conductivity of water and water based liquids.

Commercial parylene coating equipment, for instance, the equipment from VSi-PARYLENE, can possess a chamber size as large as 24″ (in diameter)×28″ (in height) which can be used to coat large parts with parylene through chemical vapor deposition (CVD). Prior to parylene CVD, a silane adhesion promoter can be applied to pre-cleaned parts prior to parylene coating. Parylene is the common name of a family of polymers which can be obtained by polymerization of para-xylylene. It is known to be able to achieve pin-hole free coatings even in tiny gaps between chips and substrates. It can penetrate into tiny, deep crevices as small as 0.1 um or smaller in opening size on exposed part surfaces. Parylene has excellent electrical insulation properties and is often applied as an excellent conformal coating. Parylene possesses an ultra-high dielectric strength of 220 kV/mm-276 kV/mm, far higher than 20 kV/mm for epoxies (and that for AlN) and is stable up to 420° C. Certain varieties of parylene (e.g., parylene AF-4) is thermally stable for up to 10 years at a long-term temperature limit of 350° C. Parylene can also be an extremely effective moisture and chemical barrier. It can be etched using dry etching such as plasma etching, reactive ion etching or deep reactive ion etching (e.g., using SF_(e) optimized O₂ plasma etching). Besides using parylene as a thin conformal coating material, GVD corporation also markets an alternative thin CVD conformal coating material which can also be considered particularly for high-frequency RF applications. This material likely has to do with a precursor gas that consists of an initiator and at least one monomer comprising a cyclic siloxane and at least two vinyl groups, and depositing a polymer formed from at least one monomer on the part to be coated. Non-polymeric conformal coating materials such as ceramic insulators including TiO₂ and HfO₂ may also be considered.

Although direct-to-chip liquid cooling is used for demonstration in FIGS. 39 to 44 and air cooling in FIGS. 45 and 46 , these 3D cooling structures can be extended to liquid immersion cooling with modifications.

It will be apparent to those skilled in the art that various modifications and variations could be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents. 

What is claimed is:
 1. A semiconductor structure, comprising: a substrate; and a first circuit containing composite block over the substrate; wherein the first circuit containing composite block comprises a through via therein and a re-distribution layer thereon; and wherein the first circuit containing composite block comprises a semiconductor block and a diamond block.
 2. The semiconductor structure in claim 1, further comprising a second circuit containing composite block under the first circuit containing composite block; wherein the second circuit containing composite block comprises a through via therein and a re-distribution layer thereon; and wherein the second circuit containing composite block comprises a semiconductor block and/or a diamond block.
 3. The semiconductor structure in claim 2, wherein the first circuit containing composite block or the second circuit containing composite block further comprises a plurality of IC circuits.
 4. The semiconductor structure in claim 1, wherein the through via is an electrical via, an optical via, a thermal via or a fluidic via.
 5. The method in claim 1, wherein the re-distribution layer comprises an electrical interconnection or an optical waveguide.
 6. A semiconductor structure, comprising: a substrate; a first circuit containing composite block over the substrate; wherein the first circuit containing composite block comprises a first semiconductor block and a first diamond block, the first circuit containing composite block comprises a first through via therein, and a first set of IC circuit in the first semiconductor block; and a cold plate bonded to the first circuit containing composite block.
 7. The semiconductor structure in claim 6, further comprising an interposer above the substrate and under the first circuit containing composite block, wherein the interposer comprises a fluidic via.
 8. The semiconductor structure in claim 7, further comprising a second circuit containing composite block bonded to the first circuit containing composite block; wherein the second circuit containing composite block comprises a second semiconductor block and a second diamond block, and the second circuit containing composite block comprises a second through via therein.
 9. The semiconductor structure in claim 8, wherein a diamond layer is between the cold plate and the first circuit containing composite block.
 10. The semiconductor structure in claim 8, further comprising a structural member surrounding the first circuit containing composite block and the second circuit containing composite block, wherein the structural member comprises a fluidic channel fluidly coupled to the fluidic via of the interposer.
 11. The semiconductor structure in claim 10, further comprising a micro-jet coupled to the first circuit containing composite block.
 12. The semiconductor structure in claim 10, further comprising a dielectric liquid coolant filled between the structural member and the first circuit containing composite block.
 13. The semiconductor structure in claim 11, wherein the second circuit containing composite block bonded to the first circuit containing composite block through oxide-to-oxide bonding or polyimide (PI)-to-PI bonding.
 14. A semiconductor structure, comprising: a substrate; a first semiconductor block over the substrate, wherein the first semiconductor block comprises a first set of IC circuit; a second semiconductor block bonded to the first semiconductor block, wherein the second semiconductor block comprises a second set of IC circuit; and an interposer above the substrate and under the second semiconductor block, wherein the interposer comprises a fluidic via.
 15. The semiconductor structure in claim 14, further comprising a cold plate bonded to the first semiconductor block.
 16. A semiconductor structure, comprising: a substrate; a first semiconductor block over the substrate, wherein the first semiconductor block comprises a first set of IC circuit and a first fluidic channel; and a second semiconductor block bonded to the first semiconductor block, wherein the second semiconductor block comprises a second set of IC circuit and a second fluidic channel.
 17. The semiconductor structure in claim 16, further comprising a cold plate bonded to the first semiconductor block.
 18. A semiconductor structure, comprising: a substrate; a first circuit containing composite block over the substrate, wherein the first circuit containing composite block comprises a first semiconductor block and a first diamond block, and the first circuit containing composite block comprises a first through via therein, and a first set of IC circuit in the first semiconductor block; a second circuit containing composite block bonded to the first circuit containing composite block; wherein the second circuit containing composite block comprises a second semiconductor block and a second diamond block, the second circuit containing composite block comprises a second through via therein, and a second set of IC circuit in the second semiconductor block; and an interposer above the substrate and under the second circuit containing composite block, wherein the interposer comprises a third semiconductor block and a third diamond block, the interposer comprises a third through via therein, and a re-distribution layer thereon; wherein the re-distribution layer is electrically or optically coupled to the second circuit containing composite block.
 19. The semiconductor structure in claim 18, further comprising a structural member surrounding the first circuit containing composite block and the second circuit containing composite block.
 20. The semiconductor structure in claim 19, further comprising a lid joined to the semiconductor structural member.
 21. The semiconductor structure in claim 20, further comprising a diamond layer between the lid and the first circuit containing composite block. 